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| author | Michael Brown <mcb30@ipxe.org> | 2019-04-22 14:43:23 +0100 |
|---|---|---|
| committer | Michael Brown <mcb30@ipxe.org> | 2019-04-24 11:41:38 +0100 |
| commit | afee77d816f42c7e405c065395c6a7f4dc2aade1 (patch) | |
| tree | d7a248ae2c5039622e5bbbee98fb31d0b65e7fc0 /src/include/ipxe/pci.h | |
| parent | ebf2eaf515e46abd43bc798e7e4ba77bfe529218 (diff) | |
| download | ipxe-afee77d816f42c7e405c065395c6a7f4dc2aade1.zip ipxe-afee77d816f42c7e405c065395c6a7f4dc2aade1.tar.gz ipxe-afee77d816f42c7e405c065395c6a7f4dc2aade1.tar.bz2 | |
[pci] Add support for PCI MSI-X interrupts
The Intel 40 Gigabit Ethernet virtual functions support only MSI-X
interrupts, and will write back completed interrupt descriptors only
when the device attempts to raise an interrupt (or when a complete
cacheline of receive descriptors has been completed).
We cannot actually use MSI-X interrupts within iPXE, since we never
have ownership of the APIC. However, an MSI-X interrupt is
fundamentally just a DMA write of a single dword to an arbitrary
address. We can therefore configure the device to "raise" an
interrupt by writing a meaningless value to an otherwise unused memory
location: this is sufficient to trigger the receive descriptor
writeback logic.
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/include/ipxe/pci.h')
| -rw-r--r-- | src/include/ipxe/pci.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/include/ipxe/pci.h b/src/include/ipxe/pci.h index ddd8c8d..272c4c0 100644 --- a/src/include/ipxe/pci.h +++ b/src/include/ipxe/pci.h @@ -94,6 +94,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); #define PCI_CAP_ID_VPD 0x03 /**< Vital product data */ #define PCI_CAP_ID_VNDR 0x09 /**< Vendor-specific */ #define PCI_CAP_ID_EXP 0x10 /**< PCI Express */ +#define PCI_CAP_ID_MSIX 0x11 /**< MSI-X */ #define PCI_CAP_ID_EA 0x14 /**< Enhanced Allocation */ /** Next capability */ @@ -109,6 +110,16 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); #define PCI_EXP_DEVCTL 0x08 #define PCI_EXP_DEVCTL_FLR 0x8000 /**< Function level reset */ +/** MSI-X interrupts */ +#define PCI_MSIX_CTRL 0x02 +#define PCI_MSIX_CTRL_ENABLE 0x8000 /**< Enable MSI-X */ +#define PCI_MSIX_CTRL_MASK 0x4000 /**< Mask all interrupts */ +#define PCI_MSIX_CTRL_SIZE(x) ( (x) & 0x07ff ) /**< Table size */ +#define PCI_MSIX_DESC_TABLE 0x04 +#define PCI_MSIX_DESC_PBA 0x08 +#define PCI_MSIX_DESC_BIR(x) ( (x) & 0x00000007 ) /**< BAR index */ +#define PCI_MSIX_DESC_OFFSET(x) ( (x) & 0xfffffff8 ) /**< BAR offset */ + /** Uncorrectable error status */ #define PCI_ERR_UNCOR_STATUS 0x04 |