1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
|
/** @file
PAL Call Services
Copyright (c) 2006 -2007, Intel Corporation All rights
reserved. This program and the accompanying materials are
licensed and made available under the terms and conditions of
the BSD License which accompanies this distribution. The full
text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: PalCallLib.h
**/
#ifndef __PAL_CALL_LIB_H__
#define __PAL_CALL_LIB_H__
//
// CacheType of PAL_CACHE_FLUSH.
//
#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
#define PAL_CACHE_FLUSH_DATA_ALL 2
#define PAL_CACHE_FLUSH_ALL 3
#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
//
// Bitmask of Opearation of PAL_CACHE_FLUSH.
//
#define PAL_CACHE_FLUSH_INVIDED_LINES BIT0
#define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1
/**
PAL Procedure - PAL_CACHE_FLUSH.
Flush the instruction or data caches. It is required by IPF.
The PAL procedure supports the Static Registers calling
convention. It could be called at virtual mode and physical
mode.
@param Index Index of PAL_CACHE_FLUSH within the
list of PAL procedures.
@param CacheType Unsigned 64-bit integer indicating
which cache to flush.
@param Operation Formatted bit vector indicating the
operation of this call.
@param ProgressIndicator Unsigned 64-bit integer specifying
the starting position of the flush
operation.
@return R9 Unsigned 64-bit integer specifying the vector
number of the pending interrupt.
@return R10 Unsigned 64-bit integer specifying the
starting position of the flush operation.
@return R11 Unsigned 64-bit integer specifying the vector
number of the pending interrupt.
@return Status 2 - Call completed without error, but a PMI
was taken during the execution of this
procedure.
@return Status 1 - Call has not completed flushing due to
a pending interrupt.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error
**/
#define PAL_CACHE_FLUSH 1
//
// Attributes of PAL_CACHE_CONFIG_INFO1
//
#define PAL_CACHE_ATTR_WT 0
#define PAL_CACHE_ATTR_WB 1
//
// PAL_CACHE_CONFIG_INFO1.StoreHint
//
#define PAL_CACHE_STORE_TEMPORAL 0
#define PAL_CACHE_STORE_NONE_TEMPORAL 3
//
// PAL_CACHE_CONFIG_INFO1.StoreHint
//
#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
//
// PAL_CACHE_CONFIG_INFO1.StoreHint
//
#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
//
// Detail the characteristics of a given processor controlled
// cache in the cache hierarchy.
//
typedef struct {
UINT64 IsUnified : 1;
UINT64 Attributes : 2;
UINT64 Associativity:8;
UINT64 LineSize:8;
UINT64 Stride:8;
UINT64 StoreLatency:8;
UINT64 StoreHint:8;
UINT64 LoadHint:8;
} PAL_CACHE_INFO_RETURN1;
//
// Detail the characteristics of a given processor controlled
// cache in the cache hierarchy.
//
typedef struct {
UINT64 CacheSize:32;
UINT64 AliasBoundary:8;
UINT64 TagLsBits:8;
UINT64 TagMsBits:8;
} PAL_CACHE_INFO_RETURN2;
/**
PAL Procedure - PAL_CACHE_INFO.
Return detailed instruction or data cache information. It is
required by IPF. The PAL procedure supports the Static
Registers calling convention. It could be called at virtual
mode and physical mode.
@param Index Index of PAL_CACHE_INFO within the list of
PAL procedures.
@param CacheLevel Unsigned 64-bit integer specifying the
level in the cache hierarchy for which
information is requested. This value must
be between 0 and one less than the value
returned in the cache_levels return value
from PAL_CACHE_SUMMARY.
@param CacheType Unsigned 64-bit integer with a value of 1
for instruction cache and 2 for data or
unified cache. All other values are
reserved.
@param Reserved Should be 0.
@return R9 Detail the characteristics of a given
processor controlled cache in the cache
hierarchy. See PAL_CACHE_INFO_RETURN1.
@return R10 Detail the characteristics of a given
processor controlled cache in the cache
hierarchy. See PAL_CACHE_INFO_RETURN2.
@return R11 Reserved with 0.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error
**/
#define PAL_CACHE_INFO 2
//
// Level of PAL_CACHE_INIT.
//
#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
//
// Restrict of PAL_CACHE_INIT.
//
#define PAL_CACHE_INIT_NO_RESTRICT 0
#define PAL_CACHE_INIT_RESTRICTED 1
/**
PAL Procedure - PAL_CACHE_INIT.
Initialize the instruction or data caches. It is required by
IPF. The PAL procedure supports the Static Registers calling
convention. It could be called at physical mode.
@param Index Index of PAL_CACHE_INIT within the list of PAL
procedures.
@param Level Unsigned 64-bit integer containing the level of
cache to initialize. If the cache level can be
initialized independently, only that level will
be initialized. Otherwise
implementation-dependent side-effects will
occur.
@param CacheType Unsigned 64-bit integer with a value of 1 to
initialize the instruction cache, 2 to
initialize the data cache, or 3 to
initialize both. All other values are
reserved.
@param Restrict Unsigned 64-bit integer with a value of 0 or
1. All other values are reserved. If
restrict is 1 and initializing the specified
level and cache_type of the cache would
cause side-effects, PAL_CACHE_INIT will
return -4 instead of initializing the cache.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -4 - Call could not initialize the specified
level and cache_type of the cache without
side-effects and restrict was 1.
**/
#define PAL_CACHE_INIT 3
//
// PAL_CACHE_PROTECTION.Method.
//
#define PAL_CACHE_PROTECTION_NONE_PROTECT 0
#define PAL_CACHE_PROTECTION_ODD_PROTECT 1
#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
#define PAL_CACHE_PROTECTION_ECC_PROTECT 3
//
// PAL_CACHE_PROTECTION.TagOrData.
//
#define PAL_CACHE_PROTECTION_PROTECT_DATA 0
#define PAL_CACHE_PROTECTION_PROTECT_TAG 1
#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
//
// 32-bit protection information structures.
//
typedef struct {
UINT32 DataBits:8;
UINT32 TagProtLsb:6;
UINT32 TagProtMsb:6;
UINT32 ProtBits:6;
UINT32 Method:4;
UINT32 TagOrData:2;
} PAL_CACHE_PROTECTION;
/**
PAL Procedure - PAL_CACHE_PROT_INFO.
Return instruction or data cache protection information. It is
required by IPF. The PAL procedure supports the Static
Registers calling convention. It could be called at physical
mode and Virtual mode.
@param Index Index of PAL_CACHE_PROT_INFO within the list of
PAL procedures.
@param CacheLevel Unsigned 64-bit integer specifying the level
in the cache hierarchy for which information
is requested. This value must be between 0
and one less than the value returned in the
cache_levels return value from
PAL_CACHE_SUMMARY.
@param CacheType Unsigned 64-bit integer with a value of 1
for instruction cache and 2 for data or
unified cache. All other values are
reserved.
@return R9 Detail the characteristics of a given
processor controlled cache in the cache
hierarchy. See PAL_CACHE_PROTECTION[0..1].
@return R10 Detail the characteristics of a given
processor controlled cache in the cache
hierarchy. See PAL_CACHE_PROTECTION[2..3].
@return R11 Detail the characteristics of a given
processor controlled cache in the cache
hierarchy. See PAL_CACHE_PROTECTION[4..5].
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_CACHE_PROT_INFO 38
/**
@param ThreadId The thread identifier of the logical
processor for which information is being
returned. This value will be unique on a per
core basis.
@param CoreId The core identifier of the logical processor
for which information is being returned.
This value will be unique on a per physical
processor package basis.
**/
typedef struct {
UINT64 ThreadId : 16;
UINT64 Reserved1: 16;
UINT64 CoreId: 16;
UINT64 Reserved2: 16;
} PAL_PCOC_N_CACHE_INFO1;
/**
@param LogicalAddress Logical address: geographical address
of the logical processor for which
information is being returned. This is
the same value that is returned by the
PAL_FIXED_ADDR procedure when it is
called on the logical processor.
**/
typedef struct {
UINT64 LogicalAddress : 16;
UINT64 Reserved1: 16;
UINT64 Reserved2: 32;
} PAL_PCOC_N_CACHE_INFO2;
/**
PAL Procedure - PAL_CACHE_SHARED_INFO.
Returns information on which logical processors share caches.
It is optional. The PAL procedure supports the Static
Registers calling convention. It could be called at physical
mode and Virtual mode.
@param Index Index of PAL_CACHE_SHARED_INFO within the list
of PAL procedures.
@param CacheLevel Unsigned 64-bit integer specifying the
level in the cache hierarchy for which
information is requested. This value must
be between 0 and one less than the value
returned in the cache_levels return value
from PAL_CACHE_SUMMARY.
@param CacheType Unsigned 64-bit integer with a value of 1
for instruction cache and 2 for data or
unified cache. All other values are
reserved.
@param ProcNumber Unsigned 64-bit integer that specifies for
which logical processor information is
being requested. This input argument must
be zero for the first call to this
procedure and can be a maximum value of
one less than the number of logical
processors sharing this cache, which is
returned by the num_shared return value.
@return R9 Unsigned integer that returns the number of
logical processors that share the processor
cache level and type, for which information was
requested.
@return R10 The format of PAL_PCOC_N_CACHE_INFO1.
@return R11 The format of PAL_PCOC_N_CACHE_INFO2.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_CACHE_SHARED_INFO 43
/**
PAL Procedure - PAL_CACHE_SUMMARY.
Return a summary of the cache hierarchy. It is required by
IPF. The PAL procedure supports the Static Registers calling
convention. It could be called at physical mode and Virtual
mode.
@param Index Index of PAL_CACHE_SUMMARY within the list of
PAL procedures.
@return R9 CacheLevels Unsigned 64-bit integer denoting the
number of levels of cache
implemented by the processor.
Strictly, this is the number of
levels for which the cache
controller is integrated into the
processor (the cache SRAMs may be
external to the processor).
@return R10 UniqueCaches Unsigned 64-bit integer denoting the
number of unique caches implemented
by the processor. This has a maximum
of 2*cache_levels, but may be less
if any of the levels in the cache
hierarchy are unified caches or do
not have both instruction and data
caches.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_CACHE_SUMMARY 4
//
// Virtual Memory Attributes implemented by processor.
//
#define PAL_MEMORY_ATTR_WB 0
#define PAL_MEMORY_ATTR_WC 6
#define PAL_MEMORY_ATTR_UC 4
#define PAL_MEMORY_ATTR_UCE 5
#define PAL_MEMORY_ATTR_NATPAGE 7
/**
PAL Procedure - PAL_MEM_ATTRIB.
Return a list of supported memory attributes.. It is required
by IPF. The PAL procedure supports the Static Registers calling
convention. It could be called at physical mode and Virtual
mode.
@param Index Index of PAL_MEM_ATTRIB within the list of PAL
procedures.
@return R9 Attributes 8-bit vector of memory attributes
implemented by processor. See Virtual
Memory Attributes above.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_MEM_ATTRIB 5
/**
PAL Procedure - PAL_PREFETCH_VISIBILITY.
Used in architected sequence to transition pages from a
cacheable, speculative attribute to an uncacheable attribute.
It is required by IPF. The PAL procedure supports the Static
Registers calling convention. It could be called at physical
mode and Virtual mode.
@param Index Index of PAL_PREFETCH_VISIBILITY within the list
of PAL procedures.
@param TransitionType Unsigned integer specifying the type
of memory attribute transition that is
being performed.
@return Status 1 Call completed without error; this
call is not necessary on remote
processors.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_PREFETCH_VISIBILITY 41
/**
PAL Procedure - PAL_PTCE_INFO.
Return information needed for ptc.e instruction to purge
entire TC. It is required by IPF. The PAL procedure supports
the Static Registers calling convention. It could be called at
physical mode and Virtual mode.
@param Index Index of PAL_PTCE_INFO within the list
of PAL procedures.
@return R9 Unsigned 64-bit integer denoting the beginning
address to be used by the first PTCE instruction
in the purge loop.
@return R10 Two unsigned 32-bit integers denoting the loop
counts of the outer (loop 1) and inner (loop 2)
purge loops. count1 (loop 1) is contained in bits
63:32 of the parameter, and count2 (loop 2) is
contained in bits 31:0 of the parameter.
@return R11 Two unsigned 32-bit integers denoting the loop
strides of the outer (loop 1) and inner (loop 2)
purge loops. stride1 (loop 1) is contained in bits
63:32 of the parameter, and stride2 (loop 2) is
contained in bits 31:0 of the parameter.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_PTCE_INFO 6
/**
@param NumberSets Unsigned 8-bit integer denoting the number
of hash sets for the specified level
(1=fully associative)
@param NumberWays Unsigned 8-bit integer denoting the
associativity of the specified level
(1=direct).
@param NumberEntries Unsigned 16-bit integer denoting the
number of entries in the specified TC.
@param PageSizeIsOptimized Flag denoting whether the
specified level is optimized for
the region's preferred page size
(1=optimized) tc_pages indicates
which page sizes are usable by
this translation cache.
@param TcIsUnified Flag denoting whether the specified TC is
unified (1=unified).
@param EntriesReduction Flag denoting whether installed
translation registers will reduce
the number of entries within the
specified TC.
**/
typedef struct {
UINT64 NumberSets:8;
UINT64 NumberWays:8;
UINT64 NumberEntries:16;
UINT64 PageSizeIsOptimized:1;
UINT64 TcIsUnified:1;
UINT64 EntriesReduction:1;
} PAL_TC_INFO;
/**
PAL Procedure - PAL_VM_INFO.
Return detailed information about virtual memory features
supported in the processor. It is required by IPF. The PAL
procedure supports the Static Registers calling convention. It
could be called at physical mode and Virtual mode.
@param Index Index of PAL_VM_INFO within the list
of PAL procedures.
@param TcLevel Unsigned 64-bit integer specifying the level
in the TLB hierarchy for which information is
required. This value must be between 0 and one
less than the value returned in the
vm_info_1.num_tc_levels return value from
PAL_VM_SUMMARY.
@param TcType Unsigned 64-bit integer with a value of 1 for
instruction translation cache and 2 for data
or unified translation cache. All other values
are reserved.
@return R9 8-byte formatted value returning information
about the specified TC. See PAL_TC_INFO above.
@return R10 64-bit vector containing a bit for each page
size supported in the specified TC, where bit
position n indicates a page size of 2**n.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_VM_INFO 7
/**
PAL Procedure - PAL_VM_PAGE_SIZE.
Return virtual memory TC and hardware walker page sizes
supported in the processor. It is required by IPF. The PAL
procedure supports the Static Registers calling convention. It
could be called at physical mode and Virtual mode.
@param Index Index of PAL_VM_PAGE_SIZE within the list
of PAL procedures.
@return R9 64-bit vector containing a bit for each
architected page size that is supported for
TLB insertions and region registers.
@return R10 64-bit vector containing a bit for each
architected page size supported for TLB purge
operations.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_VM_PAGE_SIZE 34
/**
@param WalkerPresent 1-bit flag indicating whether a hardware
TLB walker is implemented (1 = walker
present).
@param WidthOfPhysicalAddress Unsigned 7-bit integer
denoting the number of bits of
physical address implemented.
@param WidthOfKey Unsigned 8-bit integer denoting the number
of bits mplemented in the PKR.key field.
@param MaxPkrIndex Unsigned 8-bit integer denoting the
maximum PKR index (number of PKRs-1).
@param HashTagId Unsigned 8-bit integer which uniquely
identifies the processor hash and tag
algorithm.
@param MaxDtrIndex Unsigned 8 bit integer denoting the
maximum data translation register index
(number of dtr entries - 1).
@param MaxItrIndex Unsigned 8 bit integer denoting the
maximum instruction translation register
index (number of itr entries - 1).
@param NumberOfUniqueTc Unsigned 8-bit integer denoting the
number of unique TCs implemented.
This is a maximum of
2*num_tc_levels.
@param NumberOfTcLevels Unsigned 8-bit integer denoting the
number of TC levels.
**/
typedef struct {
UINT64 WalkerPresent:1;
UINT64 WidthOfPhysicalAddress: 7;
UINT64 WidthOfKey:8;
UINT64 MaxPkrIndex:8;
UINT64 HashTagId:8;
UINT64 MaxDtrIndex:8;
UINT64 MaxItrIndex:8;
UINT64 NumberOfUniqueTc:8;
UINT64 NumberOfTcLevels:8;
} PAL_VM_INFO1;
/**
@param WidthOfVirtualAddress Unsigned 8-bit integer denoting
is the total number of virtual
address bits - 1.
@param WidthOfRid Unsigned 8-bit integer denoting the number
of bits implemented in the RR.rid field.
@param MaxPurgedTlbs Unsigned 16 bit integer denoting the
maximum number of concurrent outstanding
TLB purges allowed by the processor. A
value of 0 indicates one outstanding
purge allowed. A value of 216-1
indicates no limit on outstanding
purges. All other values indicate the
actual number of concurrent outstanding
purges allowed.
**/
typedef struct {
UINT64 WidthOfVirtualAddress:8;
UINT64 WidthOfRid:8;
UINT64 MaxPurgedTlbs:16;
UINT64 Reserved:32;
} PAL_VM_INFO2;
/**
PAL Procedure - PAL_VM_SUMMARY.
Return summary information about virtual memory features
supported in the processor. It is required by IPF. The PAL
procedure supports the Static Registers calling convention. It
could be called at physical mode and Virtual mode.
@param Index Index of PAL_VM_SUMMARY within the list
of PAL procedures.
@return R9 8-byte formatted value returning global virtual
memory information. See PAL_VM_INFO1 above.
@return R10 8-byte formatted value returning global virtual
memory information. See PAL_VM_INFO2 above.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_VM_SUMMARY 8
//
// Bit mask of TR_valid flag.
//
#define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0
#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1
#define PAL_TR_DIRTY_IS_VALID BIT2
#define PAL_TR_MEMORY_ATTR_IS_VALID BIT3
/**
PAL Procedure - PAL_VM_TR_READ.
Read contents of a translation register. It is required by
IPF. The PAL procedure supports the Stacked Register calling
convention. It could be called at physical mode.
@param Index Index of PAL_VM_TR_READ within the list
of PAL procedures.
@param RegNumber Unsigned 64-bit number denoting which TR to
read.
@param TrType Unsigned 64-bit number denoting whether to
read an ITR (0) or DTR (1). All other values
are reserved.
@param TrBuffer 64-bit pointer to the 32-byte memory buffer in
which translation data is returned.
@return R9 Formatted bit vector denoting which fields are
valid. See TR_valid above.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_VM_TR_READ 261
//
// Bit Mask of Processor Bus Fesatures .
//
/**
When 0, bus data errors are detected and single bit errors are
corrected. When 1, no error detection or correction is done.
**/
#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63
/**
When 0, bus address errors are signalled on the bus. When 1,
no bus errors are signalled on the bus. If Disable Bus Address
Error Checking is 1, this bit is ignored.
**/
#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62
/**
When 0, bus errors are detected, single bit errors are
corrected., and a CMCI or MCA is generated internally to the
processor. When 1, no bus address errors are detected or
corrected.
**/
#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61
/**
When 0, bus protocol errors (BINIT#) are signaled by the
processor on the bus. When 1, bus protocol errors (BINIT#) are
not signaled on the bus. If Disable Bus Initialization Event
Checking is 1, this bit is ignored.
**/
#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60
/**
When 0, bus protocol errors (BINIT#) are detected and sampled
and an MCA is generated internally to the processor. When 1,
the processor will ignore bus protocol error conditions
(BINIT#).
**/
#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59
/**
When 0, BERR# is signalled if a bus error is detected. When 1,
bus errors are not signalled on the bus.
**/
#define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58
/**
When 0, BERR# is signalled when internal processor requestor
initiated bus errors are detected. When 1, internal requester
bus errors are not signalled on the bus.
**/
#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57
/**
When 0, the processor takes an MCA if BERR# is asserted. When
1, the processor ignores the BERR# signal.
**/
#define PAL_BUS_DISABLE_ERROR_CHECK BIT56
/**
When 0, the processor asserts BINIT# if it detects a parity
error on the signals which identify the transactions to which
this is a response. When 1, the processor ignores parity on
these signals.
**/
#define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55
/**
When 0, the in-order transaction queue is limited only by the
number of hardware entries. When 1, the processor's in-order
transactions queue is limited to one entry.
**/
#define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54
/**
Enable a bus cache line replacement transaction when a cache
line in the exclusive state is replaced from the highest level
processor cache and is not present in the lower level processor
caches. When 0, no bus cache line replacement transaction will
be seen on the bus. When 1, bus cache line replacement
transactions will be seen on the bus when the above condition is
detected.
**/
#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53
/**
Enable a bus cache line replacement transaction when a cache
line in the shared or exclusive state is replaced from the
highest level processor cache and is not present in the lower
level processor caches.
When 0, no bus cache line replacement transaction will be seen
on the bus. When 1, bus cache line replacement transactions
will be seen on the bus when the above condition is detected.
**/
#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52
/**
When 0, the data bus is configured at the 2x data transfer
rate.When 1, the data bus is configured at the 1x data
transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
processor executes locked transactions atomically. When 1, the
processor masks the bus lock signal and executes locked
transactions as a non-atomic series of transactions.
**/
#define PAL_BUS_ENABLE_HALF_TRANSFER BIT30
/**
When 0, the processor will deassert bus request when finished
with each transaction. When 1, the processor will continue to
assert bus request after it has finished, if it was the last
agent to own the bus and if there are no other pending
requests.
**/
#define PAL_BUS_REQUEST_BUS_PARKING BIT29
/**
PAL Procedure - PAL_BUS_GET_FEATURES.
Return configurable processor bus interface features and their
current settings. It is required by IPF. The PAL procedure
supports the Stacked Register calling convention. It could be
called at physical mode.
@param Index Index of PAL_BUS_GET_FEATURES within the list
of PAL procedures.
@return R9 64-bit vector of features implemented.
(1=implemented, 0=not implemented)
@return R10 64-bit vector of current feature settings.
@return R11 64-bit vector of features controllable by
software. (1=controllable, 0= not controllable)
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_BUS_GET_FEATURES 9
/**
PAL Procedure - PAL_BUS_SET_FEATURES.
Enable or disable configurable features in processor bus
interface. It is required by IPF. It is required by IPF. The PAL procedure
supports the Static Registers calling convention. It could be
called at physical mode.
@param Index Index of PAL_BUS_SET_FEATURES within the list
of PAL procedures.
@param FeatureSelect 64-bit vector denoting desired state of
each feature (1=select, 0=non-select).
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_BUS_SET_FEATURES 10
/**
PAL Procedure - PAL_DEBUG_INFO.
Return the number of instruction and data breakpoint
registers. It is required by IPF. It is required by IPF. The
PAL procedure supports the Static Registers calling
convention. It could be called at physical mode and virtual
mode.
@param Index Index of PAL_DEBUG_INFO within the list of PAL
procedures.
@return R9 Unsigned 64-bit integer denoting the number of
pairs of instruction debug registers implemented
by the processor.
@return R10 Unsigned 64-bit integer denoting the number of
pairs of data debug registers implemented by the
processor.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_DEBUG_INFO 11
/**
PAL Procedure - PAL_FIXED_ADDR.
Return the fixed component of a processorĄ¯s directed address.
It is required by IPF. It is required by IPF. The PAL
procedure supports the Static Registers calling convention. It
could be called at physical mode and virtual mode.
@param Index Index of PAL_FIXED_ADDR within the list of PAL
procedures.
@return R9 Fixed geographical address of this processor.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_FIXED_ADDR 12
/**
PAL Procedure - PAL_FREQ_BASE.
Return the frequency of the output clock for use by the
platform, if generated by the processor. It is optinal. The
PAL procedure supports the Static Registers calling
convention. It could be called at physical mode and virtual
mode.
@param Index Index of PAL_FREQ_BASE within the list of PAL
procedures.
@return R9 Base frequency of the platform if generated by the
processor chip.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_FREQ_BASE 13
/**
PAL Procedure - PAL_FREQ_RATIOS.
Return ratio of processor, bus, and interval time counter to
processor input clock or output clock for platform use, if
generated by the processor. It is required by IPF. The PAL
procedure supports the Static Registers calling convention. It
could be called at physical mode and virtual mode.
@param Index Index of PAL_FREQ_RATIOS within the list of PAL
procedures.
@return R9 Ratio of the processor frequency to the input
clock of the processor, if the platform clock is
generated externally or to the output clock to the
platform, if the platform clock is generated by
the processor.
@return R10 Ratio of the bus frequency to the input clock of
the processor, if the platform clock is generated
externally or to the output clock to the platform,
if the platform clock is generated by the
processor.
@return R11 Ratio of the interval timer counter rate to input
clock of the processor, if the platform clock is
generated externally or to the output clock to the
platform, if the platform clock is generated by
the processor.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_FREQ_RATIOS 14
/**
@param NumberOfLogicalProcessors Total number of logical
processors on this physical
processor package that are
enabled.
@param ThreadsPerCore Number of threads per core.
@param CoresPerProcessor Total number of cores on this
physical processor package.
@param PhysicalProcessorPackageId Physical processor package
identifier which was
assigned at reset by the
platform or bus
controller. This value may
or may not be unique
across the entire platform
since it depends on the
platform vendor's policy.
**/
typedef struct {
UINT64 NumberOfLogicalProcessors:16;
UINT64 ThreadsPerCore:8;
UINT64 Reserved1:8;
UINT64 CoresPerProcessor;
UINT64 Reserved2:8;
UINT64 PhysicalProcessorPackageId:8;
UINT64 Reserved3:8;
} PAL_LOGICAL_PROCESSPR_OVERVIEW;
/**
@param ThreadId The thread identifier of the logical
processor for which information is being
returned. This value will be unique on a per
core basis.
@param CoreId The core identifier of the logical processor
for which information is being returned.
This value will be unique on a per physical
processor package basis.
**/
typedef struct {
UINT64 ThreadId:16;
UINT64 Reserved1:16;
UINT64 CoreId:16;
UINT64 Reserved2:16;
} PAL_LOGICAL_PROCESSORN_INFO1;
/**
@param LogicalAddress Geographical address of the logical
processor for which information is being
returned. This is the same value that is
returned by the PAL_FIXED_ADDR procedure
when it is called on the logical
processor.
**/
typedef struct {
UINT64 LogicalAddress:16;
UINT64 Reserved:48;
} PAL_LOGICAL_PROCESSORN_INFO2;
/**
PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
Return information on which logical processors map to a
physical processor die. It is optinal. The PAL procedure
supports the Static Registers calling convention. It could be
called at physical mode and virtual mode.
@param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
procedures.
@param ProcessorNumber Signed 64-bit integer that specifies
for which logical processor
information is being requested. When
this input argument is -1, information
is returned about the logical
processor on which the procedure call
is made. This input argument must be
in the range of 1 up to one less than
the number of logical processors
returned by num_log in the
log_overview return value.
@return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
@return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.
@return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_LOGICAL_TO_PHYSICAL 42
/**
@param NumberOfPmcPairs Unsigned 8-bit number defining the
number of generic PMC/PMD pairs.
@param WidthOfCounter Unsigned 8-bit number in the range
0:60 defining the number of
implemented counter bits.
@param TypeOfCycleCounting Unsigned 8-bit number defining the
event type for counting processor
cycles.
@param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit
number defining the
event type for retired
instruction bundles.
**/
typedef struct {
UINT64 NumberOfPmcPairs:8;
UINT64 WidthOfCounter:8;
UINT64 TypeOfCycleCounting:8;
UINT64 TypeOfRetiredInstructionBundle:8;
UINT64 Reserved:32;
} PAL_PERFORMANCE_INFO;
/**
PAL Procedure - PAL_PERF_MON_INFO.
Return the number and type of performance monitors. It is
required by IPF. The PAL procedure supports the Static
Registers calling convention. It could be called at physical
mode and virtual mode.
@param Index Index of PAL_PERF_MON_INFO within the list of
PAL procedures.
@param PerformanceBuffer An address to an 8-byte aligned
128-byte memory buffer.
@return R9 Information about the performance monitors
implemented. See PAL_PERFORMANCE_INFO;
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_PERF_MON_INFO 15
/**
PAL Procedure - PAL_PLATFORM_ADDR.
Specify processor interrupt block address and I/O port space
address. It is required by IPF. The PAL procedure supports the
Static Registers calling convention. It could be called at
physical mode and virtual mode.
@param Index Index of PAL_PLATFORM_ADDR within the list of
PAL procedures.
@param Type Unsigned 64-bit integer specifying the type of
block. 0 indicates that the processor interrupt
block pointer should be initialized. 1 indicates
that the processor I/O block pointer should be
initialized.
@param Address Unsigned 64-bit integer specifying the address
to which the processor I/O block or interrupt
block shall be set. The address must specify
an implemented physical address on the
processor model, bit 63 is ignored.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure.
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_PLATFORM_ADDR 16
/**
@param EnableBerrPromotion Bit63. Enable BERR promotion. When
1, the Bus Error (BERR) signal is
promoted to the Bus Initialization
(BINIT) signal, and the BINIT pin
is asserted on the occurrence of
each Bus Error. Setting this bit
has no effect if BINIT signalling
is disabled. (See
PAL_BUS_GET/SET_FEATURES)
@param EnableMcaPromotion Bit62, Enable MCA promotion. When
1, machine check aborts (MCAs) are
promoted to the Bus Error signal,
and the BERR pin is assert on each
occurrence of an MCA. Setting this
bit has no effect if BERR
signalling is disabled. (See
PAL_BUS_GET/SET_FEATURES)
@param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT
promotion. When 1, machine
check aborts (MCAs) are
promoted to the Bus
Initialization signal, and
the BINIT pin is assert on
each occurrence of an MCA.
Setting this bit has no
effect if BINIT signalling
is disabled. (See
PAL_BUS_GET/SET_FEATURES)
@param EnableCmciPromotion Bit60, Enable CMCI promotion When
1, Corrected Machine Check
Interrupts (CMCI) are promoted to
MCAs. They are also further
promoted to BERR if bit 39, Enable
MCA promotion, is also set and
they are promoted to BINIT if bit
38, Enable MCA to BINIT promotion,
is also set. This bit has no
effect if MCA signalling is
disabled (see
PAL_BUS_GET/SET_FEATURES)
@param DisableCache Bit59, Disable Cache. When 0, the
processor performs cast outs on
cacheable pages and issues and responds
to coherency requests normally. When 1,
the processor performs a memory access
for each reference regardless of cache
contents and issues no coherence
requests and responds as if the line
were not present. Cache contents cannot
be relied upon when the cache is
disabled. WARNING: Semaphore
instructions may not be atomic or may
cause Unsupported Data Reference faults
if caches are disabled.
@param DisableCoherency Bit58, Disable Coherency. When 0,
the processor uses normal coherency
requests and responses. When 1, the
processor answers all requests as if
the line were not present.
@param DisableDPM Bit57, Disable Dynamic Power Management
(DPM). When 0, the hardware may reduce
power consumption by removing the clock
input from idle functional units. When 1,
all functional units will receive clock
input, even when idle.
@param DisableBinitWithTimeout Bit56, Disable a BINIT on
internal processor time-out.
When 0, the processor may
generate a BINIT on an
internal processor time-out.
When 1, the processor will not
generate a BINIT on an
internal processor time-out.
The event is silently ignored.
@param EnableEnvNotification Bit55, Enable external
notification when the processor
detects hardware errors caused
by environmental factors that
could cause loss of
deterministic behavior of the
processor. When 1, this bit will
enable external notification,
when 0 external notification is
not provided. The type of
external notification of these
errors is processor-dependent. A
loss of processor deterministic
behavior is considered to have
occurred if these
environmentally induced errors
cause the processor to deviate
from its normal execution and
eventually causes different
behavior which can be observed
at the processor bus pins.
Processor errors that do not
have this effects (i.e.,
software induced machine checks)
may or may not be promoted
depending on the processor
implementation.
@param EnableVmsw Bit54, Enable the use of the vmsw
instruction. When 0, the vmsw instruction
causes a Virtualization fault when
executed at the most privileged level.
When 1, this bit will enable normal
operation of the vmsw instruction.
@param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling
on data-poisoning event
detection. When 0, a CMCI
will be signaled on error
detection. When 1, an MCA
will be signaled on error
detection. If this feature
is not supported, then the
corresponding argument is
ignored when calling
PAL_PROC_SET_FEATURES. Note
that the functionality of
this bit is independent of
the setting in bit 60
(Enable CMCI promotion), and
that the bit 60 setting does
not affect CMCI signaling
for data-poisoning related
events. Volume 2: Processor
Abstraction Layer 2:431
PAL_PROC_GET_FEATURES
@param DisablePState Bit52, Disable P-states. When 1, the PAL
P-state procedures (PAL_PSTATE_INFO,
PAL_SET_PSTATE, PAL_GET_PSTATE) will
return with a status of -1
(Unimplemented procedure).
@param DisableBranchPrediction Bit47, Disable Dynamic branch
prediction. When 0, the
processor may predict branch
targets and speculatively
execute, but may not commit
results. When 1, the processor
must wait until branch targets
are known to execute.
@param DisableDynamicInsCachePrefetch Bit46, Disable
DynamicInstruction Cache
Prefetch. When 0, the
processor may prefetch
into the caches any
instruction which has
not been executed, but
whose execution is
likely. When 1,
instructions may not be
fetched until needed or
hinted for execution.
(Prefetch for a hinted
branch is allowed even
when dynamic instruction
cache prefetch is
disabled.)
@param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic
Data Cache Prefetch.
When 0, the processor
may prefetch into the
caches any data which
has not been accessed
by instruction
execution, but which
is likely to be
accessed. When 1, no
data may be fetched
until it is needed for
instruction execution
or is fetched by an
lfetch instruction.
@param DisableSpontaneousDeferral Bit44, Disable Spontaneous
Deferral. When 1, the
processor may optionally
defer speculative loads
that do not encounter any
exception conditions, but
that trigger other
implementation-dependent
conditions (e.g., cache
miss). When 0, spontaneous
deferral is disabled.
@param DisableDynamicPrediction Bit43, Disable Dynamic
Predicate Prediction. When
0, the processor may predict
predicate results and
execute speculatively, but
may not commit results until
the actual predicates are
known. When 1, the processor
shall not execute predicated
instructions until the
actual predicates are known.
@param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.
Denotes whether XR1 XR3 are
implemented for machine check
recovery. This feature may only be
interrogated by PAL_PROC_GET_FEATURES.
It may not be enabled or disabled by
PAL_PROC_SET_FEATURES. The
corresponding argument is ignored.
@param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS
implemented. Denotes whether XIP, XPSR,
and XFS are implemented for machine
check recovery. This feature may only be
interrogated by PAL_PROC_GET_FEATURES.
It may not be enabled or disabled by
PAL_PROC_SET_FEATURES. The corresponding
argument is ignored.
@param NoVM Bit40, No Virtual Machine features implemented.
Denotes whether PSR.vm is implemented. This
feature may only be interrogated by
PAL_PROC_GET_FEATURES. It may not be enabled or
disabled by PAL_PROC_SET_FEATURES. The
corresponding argument is ignored.
@param NoVariablePState Bit39, No Variable P-state
performance: A value of 1, indicates
that a processor implements
techniques to optimize performance
for the given P-state power budget
by dynamically varying the
frequency, such that maximum
performance is achieved for the
power budget. A value of 0,
indicates that P-states have no
frequency variation or very small
frequency variations for their given
power budget. This feature may only
be interrogated by
PAL_PROC_GET_FEATURES. it may not be
enabled or disabled by
PAL_PROC_SET_FEATURES. The
corresponding argument is ignored.
@param NoSimpleImpInUndefinedIns Bit38, No Simple
implementation of
unimplemented instruction
addresses. Denotes how an
unimplemented instruction
address is recorded in IIP
on an Unimplemented
Instruction Address trap or
fault. When 1, the full
unimplemented address is
recorded in IIP; when 0, the
address is sign extended
(virtual addresses) or zero
extended (physical
addresses). This feature may
only be interrogated by
PAL_PROC_GET_FEATURES. It
may not be enabled or
disabled by
PAL_PROC_SET_FEATURES. The
corresponding argument is
ignored.
@param NoPresentPmi Bit37, No INIT, PMI, and LINT pins
present. Denotes the absence of INIT,
PMI, LINT0 and LINT1 pins on the
processor. When 1, the pins are absent.
When 0, the pins are present. This
feature may only be interrogated by
PAL_PROC_GET_FEATURES. It may not be
enabled or disabled by
PAL_PROC_SET_FEATURES. The corresponding
argument is ignored.
@param FaultInUndefinedIns Bit36, No Unimplemented
instruction address reported as
fault. Denotes how the processor
reports the detection of
unimplemented instruction
addresses. When 1, the processor
reports an Unimplemented
Instruction Address fault on the
unimplemented address; when 0, it
reports an Unimplemented
Instruction Address trap on the
previous instruction in program
order. This feature may only be
interrogated by
PAL_PROC_GET_FEATURES. It may not
be enabled or disabled by
PAL_PROC_SET_FEATURES. The
corresponding argument is
ignored.
**/
typedef struct {
UINT64 Reserved1:36;
UINT64 FaultInUndefinedIns:1;
UINT64 NoPresentPmi:1;
UINT64 NoSimpleImpInUndefinedIns:1;
UINT64 NoVariablePState:1;
UINT64 NoVM:1;
UINT64 NoXipXpsrXfs:1;
UINT64 NoXr1ThroughXr3:1;
UINT64 DisableDynamicPrediction:1;
UINT64 DisableSpontaneousDeferral:1;
UINT64 DisableDynamicDataCachePrefetch:1;
UINT64 DisableDynamicInsCachePrefetch:1;
UINT64 DisableBranchPrediction:1;
UINT64 Reserved2:4;
UINT64 DisablePState:1;
UINT64 EnableMcaOnDataPoisoning:1;
UINT64 EnableVmsw:1;
UINT64 EnableEnvNotification:1;
UINT64 DisableBinitWithTimeout:1;
UINT64 DisableDPM:1;
UINT64 DisableCoherency:1;
UINT64 DisableCache:1;
UINT64 EnableCmciPromotion:1;
UINT64 EnableMcaToBinitPromotion:1;
UINT64 EnableMcaPromotion:1;
UINT64 EnableBerrPromotion:1;
} PAL_PROCESSOR_FEATURES;
/**
PAL Procedure - PAL_PROC_GET_FEATURES.
Return configurable processor features and their current
setting. It is required by IPF. The PAL procedure supports the
Static Registers calling convention. It could be called at
physical mode and virtual mode.
@param Index Index of PAL_PROC_GET_FEATURES within the list of
PAL procedures.
@param Reserved Reserved parameter.
@param FeatureSet Feature set information is being requested
for.
@return R9 64-bit vector of features implemented. See
PAL_PROCESSOR_FEATURES.
@return R10 64-bit vector of current feature settings. See
PAL_PROCESSOR_FEATURES.
@return R11 64-bit vector of features controllable by
software.
@return Status 1 - Call completed without error; The
feature_set passed is not supported but a
feature_set of a larger value is supported.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -8 - feature_set passed is beyond the maximum
feature_set supported
**/
#define PAL_PROC_GET_FEATURES 17
/**
PAL Procedure - PAL_PROC_SET_FEATURES.
Enable or disable configurable processor features. It is
required by IPF. The PAL procedure supports the Static
Registers calling convention. It could be called at physical
mode.
@param Index Index of PAL_PROC_SET_FEATURES within the list of
PAL procedures.
@param FeatureSelect 64-bit vector denoting desired state of
each feature (1=select, 0=non-select).
@param FeatureSet Feature set to apply changes to. See
PAL_PROC_GET_FEATURES for more information
on feature sets.
@return Status 1 - Call completed without error; The
feature_set passed is not supported but a
feature_set of a larger value is supported
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -8 - feature_set passed is beyond the maximum
feature_set supported
**/
#define PAL_PROC_SET_FEATURES 18
//
// Value of PAL_REGISTER_INFO.InfoRequest.
//
#define PAL_APPLICATION_REGISTER_IMPLEMENTED 0
#define PAL_APPLICATION_REGISTER_READABLE 1
#define PAL_CONTROL_REGISTER_IMPLEMENTED 2
#define PAL_CONTROL_REGISTER_READABLE 3
/**
PAL Procedure - PAL_REGISTER_INFO.
Return AR and CR register information. It is required by IPF.
The PAL procedure supports the Static Registers calling
convention. It could be called at physical mode and virtual
mode.
@param Index Index of PAL_REGISTER_INFO within the list of
PAL procedures.
@param InfoRequest Unsigned 64-bit integer denoting what
register information is requested. See
PAL_REGISTER_INFO.InfoRequest above.
@return R9 64-bit vector denoting information for registers
0-63. Bit 0 is register 0, bit 63 is register 63.
@return R10 64-bit vector denoting information for registers
64-127. Bit 0 is register 64, bit 63 is register
127.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_REGISTER_INFO 39
/**
PAL Procedure - PAL_RSE_INFO.
Return RSE information. It is required by IPF. The PAL
procedure supports the Static Registers calling convention. It
could be called at physical mode and virtual mode.
@param Index Index of PAL_RSE_INFO within the list of
PAL procedures.
@param InfoRequest Unsigned 64-bit integer denoting what
register information is requested. See
PAL_REGISTER_INFO.InfoRequest above.
@return R9 Number of physical stacked general registers.
@return R10 RSE hints supported by processor.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_RSE_INFO 19
/**
@param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
number that provides identification
information about the PAL_B firmware.
@param PalVendor Is an unsigned 8-bit integer indicating the
vendor of the PAL code.
@param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
number that provides identification
information about the PAL_A firmware. In
the split PAL_A model, this return value
is the version number of the
processor-specific PAL_A. The generic
PAL_A version is not returned by this
procedure in the split PAL_A model.
**/
typedef struct {
UINT64 VersionOfPalB:16;
UINT64 Reserved1:8;
UINT64 PalVendor:8;
UINT64 VersionOfPalA:16;
UINT64 Reserved2:16;
} PAL_VERSION_INFO;
/**
PAL Procedure - PAL_VERSION.
Return version of PAL code. It is required by IPF. The PAL
procedure supports the Static Registers calling convention. It
could be called at physical mode and virtual mode.
@param Index Index of PAL_VERSION within the list of
PAL procedures.
@param InfoRequest Unsigned 64-bit integer denoting what
register information is requested. See
PAL_REGISTER_INFO.InfoRequest above.
@return R9 8-byte formatted value returning the minimum PAL
version needed for proper operation of the
processor. See PAL_VERSION_INFO above.
@return R10 8-byte formatted value returning the current PAL
version running on the processor. See
PAL_VERSION_INFO above.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_VERSION 20
//
// Vectors of PAL_MC_CLEAR_LOG.pending
//
#define PAL_MC_PENDING BIT0
#define PAL_INIT_PENDING BIT1
/**
PAL Procedure - PAL_MC_CLEAR_LOG.
Clear all error information from processor error logging
registers. It is required by IPF. The PAL procedure supports
the Static Registers calling convention. It could be called at
physical mode and virtual mode.
@param Index Index of PAL_MC_CLEAR_LOG within the list of
PAL procedures.
@return R9 64-bit vector denoting whether an event is
pending. See PAL_MC_CLEAR_LOG.pending above.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_MC_CLEAR_LOG 21
/**
PAL Procedure - PAL_MC_DRAIN.
Ensure that all operations that could cause an MCA have
completed. It is required by IPF. The PAL procedure supports
the Static Registers calling convention. It could be called at
physical mode and virtual mode.
@param Index Index of PAL_MC_DRAIN within the list of PAL
procedures.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_MC_DRAIN 22
/**
PAL Procedure - PAL_MC_DYNAMIC_STATE.
Return Processor Dynamic State for logging by SAL. It is
optional. The PAL procedure supports the Static Registers
calling convention. It could be called at physical mode.
@param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL
procedures.
@param Offset Offset of the next 8 bytes of Dynamic Processor
State to return. (multiple of 8).
@return R9 Unsigned 64-bit integer denoting bytes of Dynamic
Processor State returned.
@return R10 Next 8 bytes of Dynamic Processor State.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure.
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_MC_DYNAMIC_STATE 24
//
// Values of PAL_MC_ERROR_INFO.InfoIndex.
//
#define PAL_PROCESSOR_ERROR_MAP 0
#define PAL_PROCESSOR_STATE_PARAM 1
#define PAL_STRUCTURE_SPECIFIC_ERROR 2
/**
@param CoreId Bit3:0, Processor core ID (default is 0 for
processors with a single core)
@param ThreadId Bit7:4, Logical thread ID (default is 0 for
processors that execute a single thread)
@param InfoOfInsCache Bit11:8, Error information is
available for 1st, 2nd, 3rd, and 4th
level instruction caches.
@param InfoOfDataCache Bit15:12, Error information is
available for 1st, 2nd, 3rd, and 4th
level data/unified caches.
@param InfoOfInsTlb Bit19:16 Error information is available
for 1st, 2nd, 3rd, and 4th level
instruction TLB.
@param InfoOfDataTlb Bit23:20, Error information is available
for 1st, 2nd, 3rd, and 4th level
data/unified TLB
@param InfoOfProcessorBus Bit27:24 Error information is
available for the 1st, 2nd, 3rd,
and 4th level processor bus
hierarchy.
@param InfoOfRegisterFile Bit31:28 Error information is
available on register file
structures.
@param InfoOfMicroArch Bit47:32, Error information is
available on micro-architectural
structures.
**/
typedef struct {
UINT64 CoreId:4;
UINT64 ThreadId:4;
UINT64 InfoOfInsCache:4;
UINT64 InfoOfDataCache:4;
UINT64 InfoOfInsTlb:4;
UINT64 InfoOfDataTlb:4;
UINT64 InfoOfProcessorBus:4;
UINT64 InfoOfRegisterFile:4;
UINT64 InfoOfMicroArch:4;
UINT64 Reserved:16;
} PAL_MC_ERROR_INFO_LEVEL_INDEX;
//
// Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
//
#define PAL_ERR_INFO_BY_LEVEL_INDEX 0
#define PAL_ERR_INFO_TARGET_ADDRESS 1
#define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2
#define PAL_ERR_INFO_REPONSER_INDENTIFIER 3
#define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4
/**
@param Operation Bit3:0, Type of cache operation that caused
the machine check: 0 - unknown or internal
error 1 - load 2 - store 3 - instruction
fetch or instruction prefetch 4 - data
prefetch (both hardware and software) 5 -
snoop (coherency check) 6 - cast out
(explicit or implicit write-back of a cache
line) 7 - move in (cache line fill)
@param FailedCacheLevel Bit5:4 Level of cache where the
error occurred. A value of 0
indicates the first level of cache.
@param FailedInDataPart Bit8, Failure located in the data
part of the cache line.
@param FailedInTagPart Bit9, Failure located in the tag part
of the cache line.
@param FailedInDataCache Bit10, Failure located in the data
cache
@param FailedInInsCache Bit11, Failure located in the
instruction cache.
@param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache
line is held shared. 2 - cache line is held
exclusive. 3 - cache line is modified. All other
values are reserved.
@param MesiIsValid Bit15, The mesi field in the cache_check
parameter is valid.
@param FailedWay Bit20:16, Failure located in the way of
the cache indicated by this value.
@param WayIndexIsValid Bit21, The way and index field in the
cache_check parameter is valid.
@param MultipleBitsError Bit23, A multiple-bit error was
detected, and data was poisoned for
the corresponding cache line during
castout.
@param IndexOfCacheLineError Bit51:32, Index of the cache
line where the error occurred.
@param InstructionSet Bit54, Instruction set. If this value
is set to zero, the instruction that
generated the machine check was an
Intel Itanium instruction. If this bit
is set to one, the instruction that
generated the machine check was IA-32
instruction.
@param InstructionSetIsValid Bit55, The is field in the
cache_check parameter is valid.
@param PrivilegeLevel Bit57:56, Privilege level. The
privilege level of the instruction
bundle responsible for generating the
machine check.
@param PrivilegeLevelIsValide Bit58, The pl field of the
cache_check parameter is
valid.
@param McCorrected Bit59, Machine check corrected: This bit
is set to one to indicate that the machine
check has been corrected.
@param TargetAddressIsValid Bit60, Target address is valid:
This bit is set to one to
indicate that a valid target
address has been logged.
@param RequesterIdentifier Bit61, Requester identifier: This
bit is set to one to indicate that
a valid requester identifier has
been logged.
@param ResponserIdentifier Bit62, Responder identifier: This
bit is set to one to indicate that
a valid responder identifier has
been logged.
@param PreciseInsPointer Bit63, Precise instruction pointer.
This bit is set to one to indicate
that a valid precise instruction
pointer has been logged.
**/
typedef struct {
UINT64 Operation:4;
UINT64 FailedCacheLevel:2;
UINT64 Reserved1:2;
UINT64 FailedInDataPart:1;
UINT64 FailedInTagPart:1;
UINT64 FailedInDataCache:1;
UINT64 FailedInInsCache:1;
UINT64 Mesi:3;
UINT64 MesiIsValid:1;
UINT64 FailedWay:5;
UINT64 WayIndexIsValid:1;
UINT64 Reserved2:1;
UINT64 MultipleBitsError:1;
UINT64 Reserved3:8;
UINT64 IndexOfCacheLineError:20;
UINT64 Reserved4:2;
UINT64 InstructionSet:1;
UINT64 InstructionSetIsValid:1;
UINT64 PrivilegeLevel:2;
UINT64 PrivilegeLevelIsValide:1;
UINT64 McCorrected:1;
UINT64 TargetAddressIsValid:1;
UINT64 RequesterIdentifier:1;
UINT64 ResponserIdentifier:1;
UINT64 PreciseInsPointer:1;
} PAL_CACHE_CHECK_INFO;
/**
@param FailedSlot Bit7:0, Slot number of the translation
register where the failure occurred.
@param FailedSlotIsValid Bit8, The tr_slot field in the
TLB_check parameter is valid.
@param TlbLevel Bit11:10, The level of the TLB where the
error occurred. A value of 0 indicates the
first level of TLB
@param FailedInDataTr Bit16, Error occurred in the data
translation registers.
@param FailedInInsTr Bit17, Error occurred in the instruction
translation registers
@param FailedInDataTc Bit18, Error occurred in data
translation cache.
@param FailedInInsTc Bit19, Error occurred in the instruction
translation cache.
@param FailedOperation Bit23:20, Type of cache operation that
caused the machine check: 0 - unknown
1 - TLB access due to load instruction
2 - TLB access due to store
instruction 3 - TLB access due to
instruction fetch or instruction
prefetch 4 - TLB access due to data
prefetch (both hardware and software)
5 - TLB shoot down access 6 - TLB
probe instruction (probe, tpa) 7 -
move in (VHPT fill) 8 - purge (insert
operation that purges entries or a TLB
purge instruction) All other values
are reserved.
@param InstructionSet Bit54, Instruction set. If this value
is set to zero, the instruction that
generated the machine check was an
Intel Itanium instruction. If this bit
is set to one, the instruction that
generated the machine check was IA-32
instruction.
@param InstructionSetIsValid Bit55, The is field in the
TLB_check parameter is valid.
@param PrivelegeLevel Bit57:56, Privilege level. The
privilege level of the instruction
bundle responsible for generating the
machine check.
@param PrivelegeLevelIsValid Bit58, The pl field of the
TLB_check parameter is valid.
@param McCorrected Bit59, Machine check corrected: This bit
is set to one to indicate that the machine
check has been corrected.
@param TargetAddressIsValid Bit60, Target address is valid:
This bit is set to one to
indicate that a valid target
address has been logged.
@param RequesterIdentifier Bit61 Requester identifier: This
bit is set to one to indicate that
a valid requester identifier has
been logged.
@param ResponserIdentifier Bit62, Responder identifier: This
bit is set to one to indicate that
a valid responder identifier has
been logged.
@param PreciseInsPointer Bit63 Precise instruction pointer.
This bit is set to one to indicate
that a valid precise instruction
pointer has been logged.
**/
typedef struct {
UINT64 FailedSlot:8;
UINT64 FailedSlotIsValid:1;
UINT64 Reserved1 :1;
UINT64 TlbLevel:2;
UINT64 Reserved2 :4;
UINT64 FailedInDataTr:1;
UINT64 FailedInInsTr:1;
UINT64 FailedInDataTc:1;
UINT64 FailedInInsTc:1;
UINT64 FailedOperation:4;
UINT64 Reserved3:30;
UINT64 InstructionSet:1;
UINT64 InstructionSetIsValid:1;
UINT64 PrivelegeLevel:2;
UINT64 PrivelegeLevelIsValid:1;
UINT64 McCorrected:1;
UINT64 TargetAddressIsValid:1;
UINT64 RequesterIdentifier:1;
UINT64 ResponserIdentifier:1;
UINT64 PreciseInsPointer:1;
} PAL_TLB_CHECK_INFO;
/**
PAL Procedure - PAL_MC_ERROR_INFO.
Return Processor Machine Check Information and Processor
Static State for logging by SAL. It is required by IPF. The
PAL procedure supports the Static Registers calling
convention. It could be called at physical and virtual mode.
@param Index Index of PAL_MC_ERROR_INFO within the list of PAL
procedures.
@param InfoIndex Unsigned 64-bit integer identifying the
error information that is being requested.
See PAL_MC_ERROR_INFO.InfoIndex.
@param LevelIndex 8-byte formatted value identifying the
structure to return error information
on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
@param ErrorTypeIndex Unsigned 64-bit integer denoting the
type of error information that is
being requested for the structure
identified in LevelIndex.
@return R9 Error information returned. The format of this
value is dependant on the input values passed.
@return R10 If this value is zero, all the error information
specified by err_type_index has been returned. If
this value is one, more structure-specific error
information is available and the caller needs to
make this procedure call again with level_index
unchanged and err_type_index, incremented.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -6 - Argument was valid, but no error
information was available
**/
#define PAL_MC_ERROR_INFO 25
/**
PAL Procedure - PAL_MC_EXPECTED.
Set/Reset Expected Machine Check Indicator. It is required by
IPF. The PAL procedure supports the Static Registers calling
convention. It could be called at physical mode.
@param Index Index of PAL_MC_EXPECTED within the list of PAL
procedures.
@param Expected Unsigned integer with a value of 0 or 1 to
set or reset the hardware resource
PALE_CHECK examines for expected machine
checks.
@return R9 Unsigned integer denoting whether a machine check
was previously expected.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_MC_EXPECTED 23
/**
PAL Procedure - PAL_MC_REGISTER_MEM.
Register min-state save area with PAL for machine checks and
inits. It is required by IPF. The PAL procedure supports the
Static Registers calling convention. It could be called at
physical mode.
@param Index Index of PAL_MC_REGISTER_MEM within the list of PAL
procedures.
@param Address Physical address of the buffer to be
registered with PAL.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_MC_REGISTER_MEM 27
/**
PAL Procedure - PAL_MC_RESUME.
Restore minimal architected state and return to interrupted
process. It is required by IPF. The PAL procedure supports the
Static Registers calling convention. It could be called at
physical mode.
@param Index Index of PAL_MC_RESUME within the list of PAL
procedures.
@param SetCmci Unsigned 64 bit integer denoting whether to
set the CMC interrupt. A value of 0 indicates
not to set the interrupt, a value of 1
indicated to set the interrupt, and all other
values are reserved.
@param SavePtr Physical address of min-state save area used
to used to restore processor state.
@param NewContext Unsigned 64-bit integer denoting whether
the caller is returning to a new context.
A value of 0 indicates the caller is
returning to the interrupted context, a
value of 1 indicates that the caller is
returning to a new context.
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_MC_RESUME 26
/**
PAL Procedure - PAL_HALT.
Enter the low-power HALT state or an implementation-dependent
low-power state. It is optinal. The PAL procedure supports the
Static Registers calling convention. It could be called at
physical mode.
@param Index Index of PAL_HALT within the list of PAL
procedures.
@param HaltState Unsigned 64-bit integer denoting low power
state requested.
@param IoDetailPtr 8-byte aligned physical address pointer to
information on the type of I/O
(load/store) requested.
@return R9 Value returned if a load instruction is requested
in the io_detail_ptr
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_HALT 28
/**
PAL Procedure - PAL_HALT_INFO.
Return the low power capabilities of the processor. It is
required by IPF. The PAL procedure supports the
Stacked Registers calling convention. It could be called at
physical and virtual mode.
@param Index Index of PAL_HALT_INFO within the list of PAL
procedures.
@param PowerBuffer 64-bit pointer to a 64-byte buffer aligned
on an 8-byte boundary.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_HALT_INFO 257
/**
PAL Procedure - PAL_HALT_LIGHT.
Enter the low power LIGHT HALT state. It is required by
IPF. The PAL procedure supports the Static Registers calling
convention. It could be called at physical and virtual mode.
@param Index Index of PAL_HALT_LIGHT within the list of PAL
procedures.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_HALT_LIGHT 29
/**
PAL Procedure - PAL_CACHE_LINE_INIT.
Initialize tags and data of a cache line for processor
testing. It is required by IPF. The PAL procedure supports the
Static Registers calling convention. It could be called at
physical and virtual mode.
@param Index Index of PAL_CACHE_LINE_INIT within the list of PAL
procedures.
@param Address Unsigned 64-bit integer value denoting the
physical address from which the physical page
number is to be generated. The address must be
an implemented physical address, bit 63 must
be zero.
@param DataValue 64-bit data value which is used to
initialize the cache line.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_CACHE_LINE_INIT 31
/**
PAL Procedure - PAL_CACHE_READ.
Read tag and data of a cache line for diagnostic testing. It
is optional. The PAL procedure supports the
Satcked Registers calling convention. It could be called at
physical mode.
@param Index Index of PAL_CACHE_READ within the list of PAL
procedures.
@param LineId 8-byte formatted value describing where in the
cache to read the data.
@param Address 64-bit 8-byte aligned physical address from
which to read the data. The address must be an
implemented physical address on the processor
model with bit 63 set to zero.
@return R9 Right-justified value returned from the cache
line.
@return R10 The number of bits returned in data.
@return R11 The status of the cache line.
@return Status 1 - The word at address was found in the
cache, but the line was invalid.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -5 - The word at address was not found in the
cache.
@return Status -7 - The operation requested is not supported
for this cache_type and level.
**/
#define PAL_CACHE_READ 259
/**
Write tag and data of a cache for diagnostic testing. It is
optional. The PAL procedure supports the Satcked Registers
calling convention. It could be called at physical mode.
@param Index Index of PAL_CACHE_WRITE within the list of PAL
procedures.
@param LineId 8-byte formatted value describing where in the
cache to write the data.
@param Address 64-bit 8-byte aligned physical address at
which the data should be written. The address
must be an implemented physical address on the
processor model with bit 63 set to 0.
@param Data Unsigned 64-bit integer value to write into
the specified part of the cache.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -7 - The operation requested is not supported
for this cache_type and level.
**/
#define PAL_CACHE_WRITE 260
/**
PAL Procedure - PAL_TEST_INFO.
Returns alignment and size requirements needed for the memory
buffer passed to the PAL_TEST_PROC procedure as well as
information on self-test control words for the processor self
tests. It is required by IPF. The PAL procedure supports the
Static Registers calling convention. It could be called at
physical mode.
@param Index Index of PAL_TEST_INFO within the list of PAL
procedures.
@param TestPhase Unsigned integer that specifies which phase
of the processor self-test information is
being requested on. A value of 0 indicates
the phase two of the processor self-test and
a value of 1 indicates phase one of the
processor self-test. All other values are
reserved.
@return R9 Unsigned 64-bit integer denoting the number of
bytes of main memory needed to perform the second
phase of processor self-test.
@return R10 Unsigned 64-bit integer denoting the alignment
required for the memory buffer.
@return R11 48-bit wide bit-field indicating if control of
the processor self-tests is supported and which
bits of the test_control field are defined for
use.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_TEST_INFO 37
/**
@param BufferSize Indicates the size in bytes of the memory
buffer that is passed to this procedure.
BufferSize must be greater than or equal in
size to the bytes_needed return value from
PAL_TEST_INFO, otherwise this procedure will
return with an invalid argument return
value.
@param TestPhase Defines which phase of the processor
self-tests are requested to be run. A value
of zero indicates to run phase two of the
processor self-tests. Phase two of the
processor self-tests are ones that require
external memory to execute correctly. A
value of one indicates to run phase one of
the processor self-tests. Phase one of the
processor self-tests are tests run during
PALE_RESET and do not depend on external
memory to run correctly. When the caller
requests to have phase one of the processor
self-test run via this procedure call, a
memory buffer may be needed to save and
restore state as required by the PAL calling
conventions. The procedure PAL_TEST_INFO
informs the caller about the requirements of
the memory buffer.
**/
typedef struct {
UINT64 BufferSize:56;
UINT64 TestPhase:8;
} PAL_TEST_INFO_INFO;
/**
@param TestControl This is an ordered implementation-specific
control word that allows the user control
over the length and runtime of the
processor self-tests. This control word is
ordered from the longest running tests up
to the shortest running tests with bit 0
controlling the longest running test. PAL
may not implement all 47-bits of the
test_control word. PAL communicates if a
bit provides control by placing a zero in
that bit. If a bit provides no control,
PAL will place a one in it. PAL will have
two sets of test_control bits for the two
phases of the processor self-test. PAL
provides information about implemented
test_control bits at the hand-off from PAL
to SAL for the firmware recovery check.
These test_control bits provide control
for phase one of processor self-test. It
also provides this information via the PAL
procedure call PAL_TEST_INFO for both the
phase one and phase two processor tests
depending on which information the caller
is requesting. PAL interprets these bits
as input parameters on two occasions. The
first time is when SAL passes control back
to PAL after the firmware recovery check.
The second time is when a call to
PAL_TEST_PROC is made. When PAL interprets
these bits it will only interpret
implemented test_control bits and will
ignore the values located in the
unimplemented test_control bits. PAL
interprets the implemented bits such that
if a bit contains a zero, this indicates
to run the test. If a bit contains a one,
this indicates to PAL to skip the test. If
the cs bit indicates that control is not
available, the test_control bits will be
ignored or generate an illegal argument in
procedure calls if the caller sets these
bits.
@param ControlSupport This bit defines if an implementation
supports control of the PAL self-tests
via the self-test control word. If
this bit is 0, the implementation does
not support control of the processor
self-tests via the self-test control
word. If this bit is 1, the
implementation does support control of
the processor self-tests via the
self-test control word. If control is
not supported, GR37 will be ignored at
the hand-off between SAL and PAL after
the firmware recovery check and the
PAL procedures related to the
processor self-tests may return
illegal arguments if a user tries to
use the self-test control features.
**/
typedef struct {
UINT64 TestControl:47;
UINT64 ControlSupport:1;
UINT64 Reserved:16;
} PAL_SELF_TEST_CONTROL;
/**
@param Attributes Specifies the memory attributes that are
allowed to be used with the memory buffer
passed to this procedure. The attributes
parameter is a vector where each bit
represents one of the virtual memory
attributes defined by the architecture.See
MEMORY_AATRIBUTES. The caller is required
to support the cacheable attribute for the
memory buffer, otherwise an invalid
argument will be returned.
@param TestControl Is the self-test control word
corresponding to the test_phase passed.
This test_control directs the coverage and
runtime of the processor self-tests
specified by the test_phase input
argument. Information on if this
feature is implemented and the number of
bits supported can be obtained by the
PAL_TEST_INFO procedure call. If this
feature is implemented by the processor,
the caller can selectively skip parts of
the processor self-test by setting
test_control bits to a one. If a bit has a
zero, this test will be run. The values in
the unimplemented bits are ignored. If
PAL_TEST_INFO indicated that the self-test
control word is not implemented, this
procedure will return with an invalid
argument status if the caller sets any of
the test_control bits. See
PAL_SELF_TEST_CONTROL.
**/
typedef struct {
UINT64 Attributes:8;
UINT64 Reserved:8;
UINT64 TestControl:48;
} PAL_TEST_CONTROL;
/**
PAL Procedure - PAL_TEST_PROC.
Perform late processor self test. It is required by IPF. The
PAL procedure supports the Static Registers calling
convention. It could be called at physical mode.
@param Index Index of PAL_TEST_PROC within the list of PAL
procedures.
@param TestAddress 64-bit physical address of main memory
area to be used by processor self-test.
The memory region passed must be
cacheable, bit 63 must be zero.
@param TestInfo Input argument specifying the size of the
memory buffer passed and the phase of the
processor self-test that should be run. See
PAL_TEST_INFO.
@param TestParam Input argument specifying the self-test
control word and the allowable memory
attributes that can be used with the memory
buffer. See PAL_TEST_CONTROL.
@return R9 Formatted 8-byte value denoting the state of the
processor after self-test
@return Status 1 - Call completed without error, but hardware
failures occurred during self-test.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_TEST_PROC 258
/**
@param NumberOfInterruptControllers Number of interrupt
controllers currently
enabled on the system.
@param NumberOfProcessors Number of processors currently
enabled on the system.
**/
typedef struct {
UINT32 NumberOfInterruptControllers;
UINT32 NumberOfProcessors;
} PAL_PLATFORM_INFO;
/**
PAL Procedure - PAL_COPY_INFO.
Return information needed to relocate PAL procedures and PAL
PMI code to memory. It is required by IPF. The PAL procedure
supports the Static Registers calling convention. It could be
called at physical mode.
@param Index Index of PAL_COPY_INFO within the list of PAL
procedures.
@param CopyType Unsigned integer denoting type of procedures
for which copy information is requested.
@param PlatformInfo 8-byte formatted value describing the
number of processors and the number of
interrupt controllers currently enabled
on the system. See PAL_PLATFORM_INFO.
@param McaProcStateInfo Unsigned integer denoting the number
of bytes that SAL needs for the
min-state save area for each
processor.
@return R9 Unsigned integer denoting the number of bytes of
PAL information that must be copied to main
memory.
@return R10 Unsigned integer denoting the starting alignment
of the data to be copied.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_COPY_INFO 30
/**
PAL Procedure - PAL_COPY_PAL.
Relocate PAL procedures and PAL PMI code to memory. It is
required by IPF. The PAL procedure supports the Stacked
Registers calling convention. It could be called at physical
mode.
@param Index Index of PAL_COPY_PAL within the list of PAL
procedures.
@param TargetAddress Physical address of a memory buffer to
copy relocatable PAL procedures and PAL
PMI code.
@param AllocSize Unsigned integer denoting the size of the
buffer passed by SAL for the copy operation.
@param CopyOption Unsigned integer indicating whether
relocatable PAL code and PAL PMI code
should be copied from firmware address
space to main memory.
@return R9 Unsigned integer denoting the offset of PAL_PROC
in the relocatable segment copied.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_COPY_PAL 256
/**
PAL Procedure - PAL_ENTER_IA_32_ENV.
Enter IA-32 System environment. It is optional. The PAL
procedure supports the Static Registers calling convention.
It could be called at physical mode.
Note: Since this is a special call, it does not follow the PAL
static register calling convention. GR28 contains the index of
PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
input arguments including GR29-GR31 are setup by SAL to values
as required by the IA-32 operating system defined in Table
11-67. The registers that are designated as preserved, scratch,
input arguments and procedure return values by the static
procedure calling convention are not followed by this call. For
instance, GR5 and GR6 need not be preserved since these are
regarded as scratch by the IA-32 operating system. Note: In an
MP system, this call must be COMPLETED on the first CPU to enter
the IA-32 System Environment (may or may not be the BSP) prior
to being called on the remaining processors in the MP system.
@param Index GR28 contains the index of the
PAL_ENTER_IA_32_ENV call within the list of PAL
procedures.
@return Status The status is returned in GR4.
-1 - Un-implemented procedure 0 JMPE detected
at privilege level
0 - 1 SAL allocated buffer for IA-32 System
Environment operation is too small
2 - IA-32 Firmware Checksum Error
3 - SAL allocated buffer for IA-32 System
Environment operation is not properly aligned
4 - Error in SAL MP Info Table
5 - Error in SAL Memory Descriptor Table
6 - Error in SAL System Table
7 - Inconsistent IA-32 state
8 - IA-32 Firmware Internal Error
9 - IA-32 Soft Reset (Note: remaining register
state is undefined for this termination
reason)
10 - Machine Check Error
11 - Error in SAL I/O Intercept Table
12 - Processor exit due to other processor in
MP system terminating the IA32 system
environment. (Note: remaining register state
is undefined for this termination reason.)
13 - Itanium architecture-based state
corruption by either SAL PMI handler or I/O
Intercept callback function.
**/
#define PAL_ENTER_IA_32_ENV 33
/**
PAL Procedure - PAL_PMI_ENTRYPOINT.
Register PMI memory entrypoints with processor. It is required
by IPF. The PAL procedure supports the Stacked Registers
calling convention. It could be called at physical mode.
@param Index Index of PAL_PMI_ENTRYPOINT within the list of
PAL procedures.
@param SalPmiEntry 256-byte aligned physical address of SAL
PMI entrypoint in memory.
@return Status 0 - Call completed without error
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_PMI_ENTRYPOINT 32
/**
The ASCII brand identification string will be copied to the
address specified in the address input argument. The processor
brand identification string is defined to be a maximum of 128
characters long; 127 bytes will contain characters and the 128th
byte is defined to be NULL (0). A processor may return less than
the 127 ASCII characters as long as the string is null
terminated. The string length will be placed in the brand_info
return argument.
**/
#define PAL_BRAND_INFO_ID_REQUEST 0
/**
PAL Procedure - PAL_BRAND_INFO.
Provides processor branding information. It is optional by
IPF. The PAL procedure supports the Stacked Registers calling
convention. It could be called at physical and Virtual mode.
@param Index Index of PAL_BRAND_INFO within the list of PAL
procedures.
@param InfoRequest Unsigned 64-bit integer specifying the
information that is being requested. (See
PAL_BRAND_INFO_ID_REQUEST)
@param Address Unsigned 64-bit integer specifying the
address of the 128-byte block to which the
processor brand string shall be written.
@reture R9 Brand information returned. The format of this
value is dependent on the input values passed.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -6 - Input argument is not implemented.
**/
#define PAL_BRAND_INFO 274
/**
PAL Procedure - PAL_GET_HW_POLICY.
Returns the current hardware resource sharing policy of the
processor. It is optional by IPF. The PAL procedure supports
the Static Registers calling convention. It could be called at
physical and Virtual mode.
@param Index Index of PAL_GET_HW_POLICY within the list of PAL
procedures.
@param ProcessorNumber Unsigned 64-bit integer that specifies
for which logical processor
information is being requested. This
input argument must be zero for the
first call to this procedure and can
be a maximum value of one less than
the number of logical processors
impacted by the hardware resource
sharing policy, which is returned by
the R10 return value.
@reture R9 Unsigned 64-bit integer representing the current
hardware resource sharing policy.
@return R10 Unsigned 64-bit integer that returns the number
of logical processors impacted by the policy
input argument.
@return R11 Unsigned 64-bit integer containing the logical
address of one of the logical processors
impacted by policy modification.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_GET_HW_POLICY 48
//
// Value of PAL_SET_HW_POLICY.Policy
//
#define PAL_SET_HW_POLICY_PERFORMANCE 0
#define PAL_SET_HW_POLICY_FAIRNESS 1
#define PAL_SET_HW_POLICY_HIGH_PRIORITY 2
#define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3
/**
PAL Procedure - PAL_SET_HW_POLICY.
Sets the current hardware resource sharing policy of the
processor. It is optional by IPF. The PAL procedure supports
the Static Registers calling convention. It could be called at
physical and Virtual mode.
@param Index Index of PAL_SET_HW_POLICY within the list of PAL
procedures.
@param Policy Unsigned 64-bit integer specifying the hardware
resource sharing policy the caller is setting.
See Value of PAL_SET_HW_POLICY.Policy above.
@return Status 1 - Call completed successfully but could not
change the hardware policy since a
competing logical processor is set in
exclusive high priority.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_SET_HW_POLICY 49
/**
@param Mode Bit2:0, Indicates the mode of operation for this
procedure: 0 - Query mode 1 ¨C Error inject mode
(err_inj should also be specified) 2 - Cancel
outstanding trigger. All other fields in
PAL_MC_ERROR_TYPE_INFO,
PAL_MC_ERROR_STRUCTURE_INFO and
PAL_MC_ERROR_DATA_BUFFER are ignored. All other
values are reserved.
@param ErrorInjection Bit5:3, indicates the mode of error
injection: 0 - Error inject only (no
error consumption) 1 - Error inject
and consume All other values are
reserved.
@param ErrorSeverity Bit7:6, indicates the severity desired
for error injection/query. Definitions
of the different error severity types
0 - Corrected error 1 - Recoverable
error 2 - Fatal error 3 - Reserved
@param ErrorStructure Bit12:8, Indicates the structure
identification for error
injection/query: 0 - Any structure
(cannot be used during query mode).
When selected, the structure type used
for error injection is determined by
PAL. 1 - Cache 2 - TLB 3 - Register
file 4 - Bus/System interconnect 5-15
- Reserved 16-31 - Processor
specific error injection
capabilities.ErrorDataBuffer is used
to specify error types. Please refer
to the processor specific
documentation for additional details.
@param StructureHierarchy Bit15:13, Indicates the structure
hierarchy for error
injection/query: 0 - Any level of
hierarchy (cannot be used during
query mode). When selected, the
structure hierarchy used for error
injection is determined by PAL. 1
- Error structure hierarchy
level-1 2 - Error structure
hierarchy level-2 3 - Error
structure hierarchy level-3 4 -
Error structure hierarchy level-4
All other values are reserved.
Reserved 63:16 Reserved
**/
typedef struct {
UINT64 Mode:3;
UINT64 ErrorInjection:3;
UINT64 ErrorSeverity:2;
UINT64 ErrorStructure:5;
UINT64 StructureHierarchy:3;
UINT64 Reserved:48;
} PAL_MC_ERROR_TYPE_INFO;
/**
@param StructInfoIsValid Bit0 When 1, indicates that the
structure information fields
(c_t,cl_p,cl_id) are valid and
should be used for error injection.
When 0, the structure information
fields are ignored, and the values
of these fields used for error
injection are
implementation-specific.
@param CacheType Bit2:1 Indicates which cache should be used
for error injection: 0 - Reserved 1 -
Instruction cache 2 - Data or unified cache
3 - Reserved
@param PortionOfCacheLine Bit5:3 Indicates the portion of the
cache line where the error should
be injected: 0 - Reserved 1 - Tag
2 - Data 3 - mesi All other
values are reserved.
@param Mechanism Bit8:6 Indicates which mechanism is used to
identify the cache line to be used for error
injection: 0 - Reserved 1 - Virtual address
provided in the inj_addr field of the buffer
pointed to by err_data_buffer should be used
to identify the cache line for error
injection. 2 - Physical address provided in
the inj_addr field of the buffer pointed to
by err_data_buffershould be used to identify
the cache line for error injection. 3 - way
and index fields provided in err_data_buffer
should be used to identify the cache line
for error injection. All other values are
reserved.
@param DataPoisonOfCacheLine Bit9 When 1, indicates that a
multiple bit, non-correctable
error should be injected in the
cache line specified by cl_id.
If this injected error is not
consumed, it may eventually
cause a data-poisoning event
resulting in a corrected error
signal, when the associated
cache line is cast out (implicit
or explicit write-back of the
cache line). The error severity
specified by err_sev in
err_type_info must be set to 0
(corrected error) when this bit
is set.
@param TrigerInfoIsValid Bit32 When 1, indicates that the
trigger information fields (trigger,
trigger_pl) are valid and should be
used for error injection. When 0,
the trigger information fields are
ignored and error injection is
performed immediately.
@param Triger Bit36:33 Indicates the operation type to be
used as the error trigger condition. The
address corresponding to the trigger is
specified in the trigger_addr field of the
buffer pointed to by err_data_buffer: 0 -
Instruction memory access. The trigger match
conditions for this operation type are similar
to the IBR address breakpoint match conditions
1 - Data memory access. The trigger match
conditions for this operation type are similar
to the DBR address breakpoint match conditions
All other values are reserved.
@param PrivilegeOfTriger Bit39:37 Indicates the privilege
level of the context during which
the error should be injected: 0 -
privilege level 0 1 - privilege
level 1 2 - privilege level 2 3 -
privilege level 3 All other values
are reserved. If the implementation
does not support privilege level
qualifier for triggers (i.e. if
trigger_pl is 0 in the capabilities
vector), this field is ignored and
triggers can be taken at any
privilege level.
**/
typedef struct {
UINT64 StructInfoIsValid:1;
UINT64 CacheType:2;
UINT64 PortionOfCacheLine:3;
UINT64 Mechanism:3;
UINT64 DataPoisonOfCacheLine:1;
UINT64 Reserved1:22;
UINT64 TrigerInfoIsValid:1;
UINT64 Triger:4;
UINT64 PrivilegeOfTriger:3;
UINT64 Reserved2:24;
} PAL_MC_ERROR_STRUCT_INFO;
/**
Buffer Pointed to by err_data_buffer ¨C TLB
**/
typedef struct {
UINT64 TrigerAddress;
UINT64 VirtualPageNumber:52;
UINT64 Reserved1:8;
UINT64 RegionId:24;
UINT64 Reserved2:40;
} PAL_MC_ERROR_DATA_BUFFER_TLB;
/**
PAL Procedure - PAL_MC_ERROR_INJECT.
Injects the requested processor error or returns information
on the supported injection capabilities for this particular
processor implementation. It is optional by IPF. The PAL
procedure supports the Stacked Registers calling convention.
It could be called at physical and Virtual mode.
@param Index Index of PAL_MC_ERROR_INJECT within the list of PAL
procedures.
@param ErrorTypeInfo Unsigned 64-bit integer specifying the
first level error information which
identifies the error structure and
corresponding structure hierarchy, and
the error severity.
@param ErrorStructInfo Unsigned 64-bit integer identifying
the optional structure specific
information that provides the second
level details for the requested error.
@param ErrorDataBuffer 64-bit physical address of a buffer
providing additional parameters for
the requested error. The address of
this buffer must be 8-byte aligned.
@return R9 64-bit vector specifying the supported error
injection capabilities for the input argument
combination of struct_hier, err_struct and
err_sev fields in ErrorTypeInfo.
@return R10 64-bit vector specifying the architectural
resources that are used by the procedure.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -4 - Call completed with error; the requested
error could not be injected due to failure in
locating the target location in the specified
structure.
@return Status -5 - Argument was valid, but requested error
injection capability is not supported.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_MC_ERROR_INJECT 276
//
// Types of PAL_GET_PSTATE.Type
//
#define PAL_GET_PSTATE_RECENT 0
#define PAL_GET_PSTATE_AVERAGE_NEW_START 1
#define PAL_GET_PSTATE_AVERAGE 2
#define PAL_GET_PSTATE_NOW 3
/**
PAL Procedure - PAL_GET_PSTATE.
Returns the performance index of the processor. It is optional
by IPF. The PAL procedure supports the Stacked Registers
calling convention. It could be called at physical and Virtual
mode.
@param Index Index of PAL_GET_PSTATE within the list of PAL
procedures.
@param Type Type of performance_index value to be returned
by this procedure.See PAL_GET_PSTATE.Type above.
@return R9 Unsigned integer denoting the processor
performance for the time duration since the last
PAL_GET_PSTATE procedure call was made. The
value returned is between 0 and 100, and is
relative to the performance index of the highest
available P-state.
@return Status 1 - Call completed without error, but accuracy
of performance index has been impacted by a
thermal throttling event, or a
hardware-initiated event.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_GET_PSTATE 262
/**
Layout of PAL_PSTATE_INFO.PStateBuffer
**/
typedef struct {
UINT32 PerformanceIndex:7;
UINT32 Reserved1:5;
UINT32 TypicalPowerDissipation:20;
UINT32 TransitionLatency1;
UINT32 TransitionLatency2;
UINT32 Reserved2;
} PAL_PSTATE_INFO_BUFFER;
/**
PAL Procedure - PAL_PSTATE_INFO.
Returns information about the P-states supported by the
processor. It is optional by IPF. The PAL procedure supports
the Static Registers calling convention. It could be called
at physical and Virtual mode.
@param Index Index of PAL_PSTATE_INFO within the list of PAL
procedures.
@param PStateBuffer 64-bit pointer to a 256-byte buffer
aligned on an 8-byte boundary. See
PAL_PSTATE_INFO_BUFFER above.
@return R9 Unsigned integer denoting the number of P-states
supported. The maximum value of this field is 16.
@return R10 Dependency domain information
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
**/
#define PAL_PSTATE_INFO 44
/**
PAL Procedure - PAL_SET_PSTATE.
To request a processor transition to a given P-state. It is
optional by IPF. The PAL procedure supports the Stacked
Registers calling convention. It could be called at physical
and Virtual mode.
@param Index Index of PAL_SET_PSTATE within the list of PAL
procedures.
@param PState Unsigned integer denoting the processor
P-state being requested.
@param ForcePState Unsigned integer denoting whether the
P-state change should be forced for the
logical processor.
@return Status 1 - Call completed without error, but
transition request was not accepted
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_SET_PSTATE 263
/**
PAL Procedure - PAL_SHUTDOWN.
Put the logical processor into a low power state which can be
exited only by a reset event. It is optional by IPF. The PAL
procedure supports the Static Registers calling convention. It
could be called at physical mode.
@param Index Index of PAL_SHUTDOWN within the list of PAL
procedures.
@param NotifyPlatform 8-byte aligned physical address
pointer providing details on how to
optionally notify the platform that
the processor is entering a shutdown
state.
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_SHUTDOWN 45
/**
Layout of PAL_MEMORY_BUFFER.ControlWord
**/
typedef struct {
UINT64 Registration:1;
UINT64 ProbeInterrupt:1;
UINT64 Reserved:62;
} PAL_MEMORY_CONTROL_WORD;
/**
PAL Procedure - PAL_MEMORY_BUFFER.
Provides cacheable memory to PAL for exclusive use during
runtime. It is optional by IPF. The PAL procedure supports the
Static Registers calling convention. It could be called at
physical mode.
@param Index Index of PAL_MEMORY_BUFFER within the list of PAL
procedures.
@param BaseAddress Physical address of the memory buffer
allocated for PAL use.
@param AllocSize Unsigned integer denoting the size of the
memory buffer.
@param ControlWord Formatted bit vector that provides control
options for this procedure. See
PAL_MEMORY_CONTROL_WORD above.
@return R9 Returns the minimum size of the memory buffer
required if the alloc_size input argument was
not large enough.
@return Status 1 - Call has not completed a buffer relocation
due to a pending interrupt
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_MEMORY_BUFFER 277
/**
PAL Procedure - PAL_VP_CREATE.
Initializes a new vpd for the operation of a new virtual
processor in the virtual environment. It is optional by IPF.
The PAL procedure supports the Stacked Registers calling
convention. It could be called at Virtual mode.
@param Index Index of PAL_VP_CREATE within the list of PAL
procedures.
@param Vpd 64-bit host virtual pointer to the Virtual
Processor Descriptor (VPD).
@param HostIva 64-bit host virtual pointer to the host IVT
for the virtual processor
@param OptionalHandler 64-bit non-zero host-virtual pointer
to an optional handler for
virtualization intercepts.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_VP_CREATE 265
/**
Virtual Environment Information Parameter
**/
typedef struct {
UINT64 Reserved1:8;
UINT64 Opcode:1;
UINT64 Reserved:53;
} PAL_VP_ENV_INFO_RETURN;
/**
PAL Procedure - PAL_VP_ENV_INFO.
Returns the parameters needed to enter a virtual environment.
It is optional by IPF. The PAL procedure supports the Stacked
Registers calling convention. It could be called at Virtual
mode.
@param Index Index of PAL_VP_ENV_INFO within the list of PAL
procedures.
@param Vpd 64-bit host virtual pointer to the Virtual
Processor Descriptor (VPD).
@param HostIva 64-bit host virtual pointer to the host IVT
for the virtual processor
@param OptionalHandler 64-bit non-zero host-virtual pointer
to an optional handler for
virtualization intercepts.
@return R9 Unsigned integer denoting the number of bytes
required by the PAL virtual environment buffer
during PAL_VP_INIT_ENV
@return R10 64-bit vector of virtual environment
information. See PAL_VP_ENV_INFO_RETURN.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_VP_ENV_INFO 266
/**
PAL Procedure - PAL_VP_EXIT_ENV.
Allows a logical processor to exit a virtual environment.
It is optional by IPF. The PAL procedure supports the Stacked
Registers calling convention. It could be called at Virtual
mode.
@param Index Index of PAL_VP_EXIT_ENV within the list of PAL
procedures.
@param Iva Optional 64-bit host virtual pointer to the IVT
when this procedure is done
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_VP_EXIT_ENV 267
/**
PAL Procedure - PAL_VP_INIT_ENV.
Allows a logical processor to enter a virtual environment. It
is optional by IPF. The PAL procedure supports the Stacked
Registers calling convention. It could be called at Virtual
mode.
@param Index Index of PAL_VP_INIT_ENV within the list of PAL
procedures.
@param ConfigOptions 64-bit vector of global configuration
settings.
@param PhysicalBase Host physical base address of a block of
contiguous physical memory for the PAL
virtual environment buffer 1) This
memory area must be allocated by the VMM
and be 4K aligned. The first logical
processor to enter the environment will
initialize the physical block for
virtualization operations.
@param VirtualBase Host virtual base address of the
corresponding physical memory block for
the PAL virtual environment buffer : The
VMM must maintain the host virtual to host
physical data and instruction translations
in TRs for addresses within the allocated
address space. Logical processors in this
virtual environment will use this address
when transitioning to virtual mode
operations.
@return R9 Virtualization Service Address ¨C VSA specifies
the virtual base address of the PAL
virtualization services in this virtual
environment.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_VP_INIT_ENV 268
/**
PAL Procedure - PAL_VP_REGISTER.
Register a different host IVT and/or a different optional
virtualization intercept handler for the virtual processor
specified by vpd. It is optional by IPF. The PAL procedure
supports the Stacked Registers calling convention. It could be
called at Virtual mode.
@param Index Index of PAL_VP_REGISTER within the list of PAL
procedures.
@param Vpd 64-bit host virtual pointer to the Virtual
Processor Descriptor (VPD) host_iva 64-bit host
virtual pointer to the host IVT for the virtual
processor
@param OptionalHandler 64-bit non-zero host-virtual pointer
to an optional handler for
virtualization intercepts.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_VP_REGISTER 269
/**
PAL Procedure - PAL_VP_RESTORE.
Restores virtual processor state for the specified vpd on the
logical processor. It is optional by IPF. The PAL procedure
supports the Stacked Registers calling convention. It could be
called at Virtual mode.
@param Index Index of PAL_VP_RESTORE within the list of PAL
procedures.
@param Vpd 64-bit host virtual pointer to the Virtual
Processor Descriptor (VPD) host_iva 64-bit host
virtual pointer to the host IVT for the virtual
processor
@param PalVector Vector specifies PAL procedure
implementation-specific state to be
restored.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_VP_RESTORE 270
/**
PAL Procedure - PAL_VP_SAVE.
Saves virtual processor state for the specified vpd on the
logical processor. It is optional by IPF. The PAL procedure
supports the Stacked Registers calling convention. It could be
called at Virtual mode.
@param Index Index of PAL_VP_SAVE within the list of PAL
procedures.
@param Vpd 64-bit host virtual pointer to the Virtual
Processor Descriptor (VPD) host_iva 64-bit host
virtual pointer to the host IVT for the virtual
processor
@param PalVector Vector specifies PAL procedure
implementation-specific state to be
restored.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_VP_SAVE 271
/**
PAL Procedure - PAL_VP_TERMINATE.
Terminates operation for the specified virtual processor. It
is optional by IPF. The PAL procedure supports the Stacked
Registers calling convention. It could be called at Virtual
mode.
@param Index Index of PAL_VP_TERMINATE within the list of PAL
procedures.
@param Vpd 64-bit host virtual pointer to the Virtual
Processor Descriptor (VPD)
@param Iva Optional 64-bit host virtual pointer to the IVT
when this procedure is done.
@return Status 0 - Call completed without error
@return Status -1 - Unimplemented procedure
@return Status -2 - Invalid argument
@return Status -3 - Call completed with error.
@return Status -9 - Call requires PAL memory buffer.
**/
#define PAL_VP_TERMINATE 272
/**
Makes a PAL procedure call.
This is a wrapper function to make a PAL procedure call. Based on the Index value,
this API will make static or stacked PAL call. Architected procedures may be designated
as required or optional. If a PAL procedure is specified as optional, a unique return
code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.
This indicates that the procedure is not present in this PAL implementation. It is the
callerĄ¯s responsibility to check for this return code after calling any optional PAL
procedure. No parameter checking is performed on the 4 input parameters, but there are
some common rules that the caller should follow when making a PAL call. Any address
passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses
may cause undefined results. For those parameters defined as reserved or some fields
defined as reserved must be zero filled or the invalid argument return value may be
returned or undefined result may occur during the execution of the procedure.
This function is only available on IPF.
@param Index - The PAL procedure Index number.
@param Arg2 - The 2nd parameter for PAL procedure calls.
@param Arg3 - The 3rd parameter for PAL procedure calls.
@param Arg4 - The 4th parameter for PAL procedure calls.
@return structure returned from the PAL Call procedure, including the status and return value.
**/
PAL_CALL_RETURN
EFIAPI
PalCall (
IN UINT64 Index,
IN UINT64 Arg2,
IN UINT64 Arg3,
IN UINT64 Arg4
);
#endif
|