From 3099db510e209195ccf662785ecae541d75e6ab8 Mon Sep 17 00:00:00 2001 From: Laszlo Ersek Date: Sat, 11 Nov 2023 00:57:45 +0100 Subject: OvmfPkg: remove PcdCsmEnable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PcdCsmEnable was introduced in commits 50f911d25d39 ("OvmfPkg: introduce PcdCsmEnable feature flag", 2020-02-05) and 75839f977d37 ("OvmfPkg/PlatformPei: detect SMRAM at default SMBASE (for real)", 2020-02-05). Remove it, and substitute constant FALSE wherever it has been evaluated thus far. Regression test: after building OVMF IA32X64 with -D SMM_REQUIRE, and booting it on Q35, the log still contains > Q35SmramAtDefaultSmbaseInitialization: SMRAM at default SMBASE found Cc: Anthony Perard Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jiewen Yao https://bugzilla.tianocore.org/show_bug.cgi?id=4588 Signed-off-by: Laszlo Ersek Message-Id: <20231110235820.644381-3-lersek@redhat.com> Reviewed-by: Jiewen Yao Reviewed-by: Ard Biesheuvel Acked-by: Corvin Köhne Acked-by: Gerd Hoffmann --- OvmfPkg/PlatformPei/MemDetect.c | 36 +++++++++++++----------------------- OvmfPkg/PlatformPei/PlatformPei.inf | 1 - 2 files changed, 13 insertions(+), 24 deletions(-) (limited to 'OvmfPkg/PlatformPei') diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index 0c755c4..493cb1f 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -89,32 +89,22 @@ Q35SmramAtDefaultSmbaseInitialization ( ) { RETURN_STATUS PcdStatus; + UINTN CtlReg; + UINT8 CtlRegVal; ASSERT (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID); - PlatformInfoHob->Q35SmramAtDefaultSmbase = FALSE; - if (FeaturePcdGet (PcdCsmEnable)) { - DEBUG (( - DEBUG_INFO, - "%a: SMRAM at default SMBASE not checked due to CSM\n", - __func__ - )); - } else { - UINTN CtlReg; - UINT8 CtlRegVal; - - CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL); - PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY); - CtlRegVal = PciRead8 (CtlReg); - PlatformInfoHob->Q35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal == - MCH_DEFAULT_SMBASE_IN_RAM); - DEBUG (( - DEBUG_INFO, - "%a: SMRAM at default SMBASE %a\n", - __func__, - PlatformInfoHob->Q35SmramAtDefaultSmbase ? "found" : "not found" - )); - } + CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL); + PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY); + CtlRegVal = PciRead8 (CtlReg); + PlatformInfoHob->Q35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal == + MCH_DEFAULT_SMBASE_IN_RAM); + DEBUG (( + DEBUG_INFO, + "%a: SMRAM at default SMBASE %a\n", + __func__, + PlatformInfoHob->Q35SmramAtDefaultSmbase ? "found" : "not found" + )); PcdStatus = PcdSetBoolS ( PcdQ35SmramAtDefaultSmbase, diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf index 3934aee..ad52be3 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -133,7 +133,6 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsSize [FeaturePcd] - gUefiOvmfPkgTokenSpaceGuid.PcdCsmEnable gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire [Ppis] -- cgit v1.1