From 1f87985ab7958664a84da78095b5892f88acf3f1 Mon Sep 17 00:00:00 2001 From: Feng Tian Date: Wed, 14 Sep 2016 09:48:40 +0800 Subject: MdeModulePkg/XhciPei:1ms delay before access MMIO reg during reset Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during HC reset. As this delay is not defined by XHCI spec, we use this workaround to fix the issue. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian Reviewed-by: Star Zeng --- MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'MdeModulePkg/Bus/Pci') diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c index a58739f..57e7070 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c @@ -407,6 +407,12 @@ XhcPeiResetHC ( } XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET); + // + // Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset. + // Otherwise there may have the timeout case happened. + // The below is a workaround to solve such problem. + // + MicroSecondDelay (1000); Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout); ON_EXIT: DEBUG ((EFI_D_INFO, "XhcPeiResetHC: %r\n", Status)); -- cgit v1.1