From 7a38ad07d0b15c9380d1671074aef20e096f3106 Mon Sep 17 00:00:00 2001
From: Chasel Chiu <chasel.chiu@intel.com>
Date: Fri, 7 Feb 2020 16:33:36 +0800
Subject: IntelFsp2Pkg/GenCfgOpt.py: Coverity scan flags issues.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1706

Issue was: invalid_operation: Invalid operation on
null-like value "Base".
Fixed it by initializing Base to 0 before entering
while loop.

Test:
Compared script output before and after this patch and
the result is identical.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
 IntelFsp2Pkg/Tools/GenCfgOpt.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'IntelFsp2Pkg')

diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index 2fa7582..d1d6901 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -1,6 +1,6 @@
 ## @ GenCfgOpt.py
 #
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -439,6 +439,7 @@ EndList
 
         MaxAlign = 32   #Default align to 32, but if there are 64 bit unit, align to 64
         SizeAlign = 0   #record the struct max align
+        Base = 0        #Starting offset of sub-structure.
         while len(DscLines):
             DscLine  = DscLines.pop(0).strip()
             Handle   = False
-- 
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