From fb493ac84ebc6860e1690770fb88183effadebfb Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Fri, 1 Jul 2022 20:24:26 +0200 Subject: ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled Some platforms may set up a preliminary ID map in flash and enter EFI with the MMU and caches enabled, as this removes a lot of the complexity around cache coherency. Let's take this into account, and avoid touching the MMU controls or perform cache invalidation when the MMU is enabled at entry. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) (limited to 'ArmPlatformPkg') diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index 9c4b25d..8b86c6e 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -58,17 +58,19 @@ CEntryPoint ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint ) { - // Data Cache enabled on Primary core when MMU is enabled. - ArmDisableDataCache (); - // Invalidate instruction cache - ArmInvalidateInstructionCache (); - // Enable Instruction Caches on all cores. - ArmEnableInstructionCache (); - - InvalidateDataCacheRange ( - (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase), - PcdGet32 (PcdCPUCorePrimaryStackSize) - ); + if (!ArmMmuEnabled ()) { + // Data Cache enabled on Primary core when MMU is enabled. + ArmDisableDataCache (); + // Invalidate instruction cache + ArmInvalidateInstructionCache (); + // Enable Instruction Caches on all cores. + ArmEnableInstructionCache (); + + InvalidateDataCacheRange ( + (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase), + PcdGet32 (PcdCPUCorePrimaryStackSize) + ); + } // // Note: Doesn't have to Enable CPU interface in non-secure world, -- cgit v1.1