From f598bf12660fc7e758710e6a484d7eea3bfee6ef Mon Sep 17 00:00:00 2001 From: oliviermartin Date: Sat, 11 Jun 2011 12:10:19 +0000 Subject: ArmPlatformPkg: Code cleaning - Fix coding style to follow EDK2 coding convention - Remove deprecated function - Remove unused PCDs git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11808 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPlatformPkg/PrePeiCore/MainMPCore.c | 89 +++++++++++++++++---------------- ArmPlatformPkg/PrePeiCore/MainUniCore.c | 53 +++++++++++--------- ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 32 +++--------- ArmPlatformPkg/PrePeiCore/PrePeiCore.h | 60 ++++++++++++++++++++++ 4 files changed, 144 insertions(+), 90 deletions(-) create mode 100644 ArmPlatformPkg/PrePeiCore/PrePeiCore.h (limited to 'ArmPlatformPkg/PrePeiCore') diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c index 2e6477d..39de31a 100644 --- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c @@ -12,13 +12,14 @@ * **/ -#include #include #include #include #include #include +#include "PrePeiCore.h" + extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable; /* @@ -32,60 +33,64 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable; */ VOID EFIAPI -secondary_main(IN UINTN CoreId) +SecondaryMain ( + IN UINTN CoreId + ) { - //Function pointer to Secondary Core entry point - VOID (*secondary_start)(VOID); - UINTN secondary_entry_addr=0; + // Function pointer to Secondary Core entry point + VOID (*secondary_start)(VOID); + UINTN secondary_entry_addr=0; - //Clear Secondary cores MailBox - ArmClearMPCoreMailbox(); + // Clear Secondary cores MailBox + ArmClearMPCoreMailbox(); - while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) { - ArmCallWFI(); - //Acknowledge the interrupt and send End of Interrupt signal. - PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/); - } + while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) { + ArmCallWFI(); + // Acknowledge the interrupt and send End of Interrupt signal. + PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/); + } - secondary_start = (VOID (*)())secondary_entry_addr; + secondary_start = (VOID (*)())secondary_entry_addr; - //Jump to secondary core entry point. - secondary_start(); + // Jump to secondary core entry point. + secondary_start(); - //the secondaries shouldn't reach here - ASSERT(FALSE); + // The secondaries shouldn't reach here + ASSERT(FALSE); } -VOID primary_main ( +VOID +EFIAPI +PrimaryMain ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint ) { - EFI_SEC_PEI_HAND_OFF SecCoreData; + EFI_SEC_PEI_HAND_OFF SecCoreData; - //Enable the GIC Distributor - PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase)); + //Enable the GIC Distributor + PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase)); - // If ArmVe has not been built as Standalone then we need to wake up the secondary cores - if (FeaturePcdGet(PcdStandalone) == FALSE) { - // Sending SGI to all the Secondary CPU interfaces - PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); - } + // If ArmVe has not been built as Standalone then we need to wake up the secondary cores + if (FeaturePcdGet(PcdStandalone) == FALSE) { + // Sending SGI to all the Secondary CPU interfaces + PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); + } - // - // Bind this information into the SEC hand-off state - // Note: this must be in sync with the stuff in the asm file - // Note also: HOBs (pei temp ram) MUST be above stack - // - SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); - SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress); - SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize); - SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack) - SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize); - SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2)); - SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2; - SecCoreData.StackBase = SecCoreData.TemporaryRamBase; - SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; + // + // Bind this information into the SEC hand-off state + // Note: this must be in sync with the stuff in the asm file + // Note also: HOBs (pei temp ram) MUST be above stack + // + SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); + SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress); + SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize); + SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack) + SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize); + SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2)); + SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2; + SecCoreData.StackBase = SecCoreData.TemporaryRamBase; + SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; - // jump to pei core entry point - (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable); + // Jump to PEI core entry point + (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable); } diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c b/ArmPlatformPkg/PrePeiCore/MainUniCore.c index 15e7629..c094945 100644 --- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c @@ -12,42 +12,47 @@ * **/ -#include #include #include #include +#include "PrePeiCore.h" + extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable; VOID EFIAPI -secondary_main(IN UINTN CoreId) +SecondaryMain ( + IN UINTN CoreId + ) { - ASSERT(FALSE); + ASSERT(FALSE); } -VOID primary_main ( +VOID +EFIAPI +PrimaryMain ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint ) { - EFI_SEC_PEI_HAND_OFF SecCoreData; - - - // - // Bind this information into the SEC hand-off state - // Note: this must be in sync with the stuff in the asm file - // Note also: HOBs (pei temp ram) MUST be above stack - // - SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); - SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress); - SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize); - SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack) - SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize); - SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2)); - SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2; - SecCoreData.StackBase = SecCoreData.TemporaryRamBase; - SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; - - // jump to pei core entry point - (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable); + EFI_SEC_PEI_HAND_OFF SecCoreData; + + + // + // Bind this information into the SEC hand-off state + // Note: this must be in sync with the stuff in the asm file + // Note also: HOBs (pei temp ram) MUST be above stack + // + SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); + SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress); + SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize); + SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack) + SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize); + SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2)); + SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2; + SecCoreData.StackBase = SecCoreData.TemporaryRamBase; + SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; + + // jump to pei core entry point + (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable); } diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index f76a1b1..5618647 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -13,29 +13,17 @@ * **/ -#include -#include #include #include #include #include #include +#include #include +#include #include -EFI_STATUS -EFIAPI -SecTemporaryRamSupport ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, - IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, - IN UINTN CopySize - ); - -VOID -SecSwitchStack ( - INTN StackDelta - ); +#include "PrePeiCore.h" EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport}; @@ -47,10 +35,6 @@ EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = { } }; -// Vector Table for Pei Phase -VOID PeiVectorTable (VOID); - - VOID CEntryPoint ( IN UINTN CoreId, @@ -64,8 +48,8 @@ CEntryPoint ( ArmInvalidateInstructionCache(); // Enable Instruction & Data caches - ArmEnableDataCache(); - ArmEnableInstructionCache(); + ArmEnableDataCache (); + ArmEnableInstructionCache (); // // Note: Doesn't have to Enable CPU interface in non-secure world, @@ -81,9 +65,9 @@ CEntryPoint ( //If not primary Jump to Secondary Main if(0 == CoreId) { //Goto primary Main. - primary_main(PeiCoreEntryPoint); + PrimaryMain (PeiCoreEntryPoint); } else { - secondary_main(CoreId); + SecondaryMain (CoreId); } // PEI Core should always load and never return @@ -101,7 +85,7 @@ SecTemporaryRamSupport ( { // // Migrate the whole temporary memory to permenent memory. - // + // CopyMem ( (VOID*)(UINTN)PermanentMemoryBase, (VOID*)(UINTN)TemporaryMemoryBase, diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h new file mode 100644 index 0000000..0f8778c --- /dev/null +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h @@ -0,0 +1,60 @@ +/** @file +* Main file supporting the transition to PEI Core in Normal World for Versatile Express +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ +#ifndef __PREPEICORE_H_ +#define __PREPEICORE_H_ + +#include +#include + + +EFI_STATUS +EFIAPI +SecTemporaryRamSupport ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ); + +VOID +SecSwitchStack ( + INTN StackDelta + ); + +// Vector Table for Pei Phase +VOID PeiVectorTable (VOID); + +VOID +EFIAPI +PrimaryMain ( + IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint + ); + +/* + * This is the main function for secondary cores. They loop around until a non Null value is written to + * SYS_FLAGS register.The SYS_FLAGS register is platform specific. + * Note:The secondary cores, while executing secondary_main, assumes that: + * : SGI 0 is configured as Non-secure interrupt + * : Priority Mask is configured to allow SGI 0 + * : Interrupt Distributor and CPU interfaces are enabled + * + */ +VOID +EFIAPI +SecondaryMain ( + IN UINTN CoreId + ); + +#endif -- cgit v1.1