From 1ad14bc86b56eb0134b1c9e504a7392e32c44ddb Mon Sep 17 00:00:00 2001 From: oliviermartin Date: Sat, 11 Jun 2011 12:06:59 +0000 Subject: ArmPlatformPkg: Unify the Secure and Normal FD and FV PCD naming With this change, we now have these following PCDs values to define the location of the Secure and Normal firmwares: - gArmTokenSpaceGuid.PcdSecureFd(BaseAddress|Size) - gArmTokenSpaceGuid.PcdSecureFv(BaseAddress|Size) - gArmTokenSpaceGuid.PcdNormalFd(BaseAddress|Size) - gArmTokenSpaceGuid.PcdNormalFv(BaseAddress|Size) git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11806 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/ArmPkg.dec | 4 ++++ ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc | 4 ---- .../ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc | 4 ---- .../ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf | 8 ++++---- .../ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf | 8 ++++---- ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf | 13 ++++++------- ArmPlatformPkg/PlatformPei/PlatformPei.c | 2 +- ArmPlatformPkg/PlatformPei/PlatformPei.inf | 10 ++++++---- ArmPlatformPkg/PrePeiCore/MainMPCore.c | 4 ++-- ArmPlatformPkg/PrePeiCore/MainUniCore.c | 4 ++-- ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S | 6 +++--- ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm | 2 +- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 4 ++-- ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf | 5 ++--- ArmPlatformPkg/Sec/Sec.c | 14 +++++++------- ArmPlatformPkg/Sec/Sec.inf | 2 +- 16 files changed, 45 insertions(+), 49 deletions(-) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 0357810..9f4673c 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -87,12 +87,16 @@ # gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016 + gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F + gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030 # # ARM Normal (or Non Secure) Firmware PCDs # gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0|UINT32|0x0000002B gArmTokenSpaceGuid.PcdNormalFdSize|0|UINT32|0x0000002C + gArmTokenSpaceGuid.PcdNormalFvBaseAddress|0|UINT32|0x0000002D + gArmTokenSpaceGuid.PcdNormalFvSize|0|UINT32|0x0000002E # System Memory (DRAM): These PCDs define the region of in-built system memory # Some platforms can get DRAM extensions, these additional regions will be declared diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc index 1439116..6fbea18 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc +++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc @@ -340,10 +340,6 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Size of SEC Stack for Normal World - # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize - gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase - gArmTokenSpaceGuid.PcdNormalFdSize|0x00100000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize - # System Memory (256MB) gArmTokenSpaceGuid.PcdSystemMemoryBase|0x70000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0x10000000 diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc index 2811f93..dcd75e0 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc +++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc @@ -344,10 +344,6 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Stack for each of the 4 CPU cores - # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize - gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase - gArmTokenSpaceGuid.PcdNormalFdSize|0x00100000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize - # System Memory (256MB) gArmTokenSpaceGuid.PcdSystemMemoryBase|0x70000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0x10000000 diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf index 1ee92ea..6e639fc 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf +++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf @@ -27,8 +27,8 @@ [FD.ArmRealViewEb_EFI] -BaseAddress = 0x40000000 # The base address of the FLASH Device. -Size = 0x00200000 # The size in bytes of the FLASH Device +BaseAddress = 0x40000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress +Size = 0x00200000|gArmTokenSpaceGuid.PcdNormalFdSize ErasePolarity = 1 BlockSize = 0x00010000 NumBlocks = 0x20 @@ -50,11 +50,11 @@ NumBlocks = 0x20 ################################################################################ 0x00000000|0x00050000 -gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize FV = FVMAIN_SEC 0x00050000|0x00100000 -gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize +gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvSize FV = FVMAIN_COMPACT ################################################################################ diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf index 5856d51..7634377 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf +++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf @@ -27,8 +27,8 @@ [FD.ArmRealViewEb_EFI] -BaseAddress = 0x40000000 # The base address of the FLASH Device. -Size = 0x00200000 # The size in bytes of the FLASH Device +BaseAddress = 0x40000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress +Size = 0x00200000|gArmTokenSpaceGuid.PcdNormalFdSize ErasePolarity = 1 BlockSize = 0x00010000 NumBlocks = 0x20 @@ -50,11 +50,11 @@ NumBlocks = 0x20 ################################################################################ 0x00000000|0x00050000 -gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize FV = FVMAIN_SEC 0x00050000|0x00100000 -gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize +gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvSize FV = FVMAIN_COMPACT ################################################################################ diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf index b344217..55e4e07 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf @@ -27,10 +27,10 @@ [FD.Sec_ArmVExpress_EFI] BaseAddress = 0x44000000|gArmTokenSpaceGuid.PcdSecureFdBaseAddress #The base address of the Secure FLASH Device. -Size = 0x00200000|gArmTokenSpaceGuid.PcdSecureFdSize #The size in bytes of the Secure FLASH Device +Size = 0x00080000|gArmTokenSpaceGuid.PcdSecureFdSize #The size in bytes of the Secure FLASH Device ErasePolarity = 1 BlockSize = 0x00001000 -NumBlocks = 0x200 +NumBlocks = 0x80 ################################################################################ # @@ -48,8 +48,8 @@ NumBlocks = 0x200 # ################################################################################ -0x00000000|0x00200000 -gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize +0x00000000|0x00080000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize FV = FVMAIN_SEC @@ -83,7 +83,7 @@ NumBlocks = 0x200 ################################################################################ 0x00000000|0x00200000 -gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize +gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvBaseSize FV = FVMAIN_COMPACT @@ -147,11 +147,10 @@ READ_LOCK_STATUS = TRUE INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf diff --git a/ArmPlatformPkg/PlatformPei/PlatformPei.c b/ArmPlatformPkg/PlatformPei/PlatformPei.c index f3e9678..4c0ae21 100644 --- a/ArmPlatformPkg/PlatformPei/PlatformPei.c +++ b/ArmPlatformPkg/PlatformPei/PlatformPei.c @@ -78,7 +78,7 @@ Returns: BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize)); - BuildFvHob (FixedPcdGet32(PcdFlashFvMainBase), FixedPcdGet32(PcdFlashFvMainSize)); + BuildFvHob (PcdGet32(PcdNormalFvBaseAddress), PcdGet32(PcdNormalFvSize)); BootMode = ArmPlatformGetBootMode (); Status = (**PeiServices).SetBootMode (PeiServices, (UINT8) BootMode); diff --git a/ArmPlatformPkg/PlatformPei/PlatformPei.inf b/ArmPlatformPkg/PlatformPei/PlatformPei.inf index c35889a..92cf3aa 100644 --- a/ArmPlatformPkg/PlatformPei/PlatformPei.inf +++ b/ArmPlatformPkg/PlatformPei/PlatformPei.inf @@ -47,10 +47,12 @@ gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED [FixedPcd] - gArmTokenSpaceGuid.PcdNormalFdBaseAddress # The base address of the FLASH Device. - gArmTokenSpaceGuid.PcdNormalFdSize # The size in bytes of the FLASH Device - gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase - gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize + gArmTokenSpaceGuid.PcdNormalFdBaseAddress + gArmTokenSpaceGuid.PcdNormalFdSize + + gArmTokenSpaceGuid.PcdNormalFvBaseAddress + gArmTokenSpaceGuid.PcdNormalFvSize + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c index 2a4ee61..2e6477d 100644 --- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c @@ -77,8 +77,8 @@ VOID primary_main ( // Note also: HOBs (pei temp ram) MUST be above stack // SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); - SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFdBaseAddress); - SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFdSize); + SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress); + SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize); SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack) SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize); SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2)); diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c b/ArmPlatformPkg/PrePeiCore/MainUniCore.c index ac7b16a..15e7629 100644 --- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c @@ -39,8 +39,8 @@ VOID primary_main ( // Note also: HOBs (pei temp ram) MUST be above stack // SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); - SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFdBaseAddress); - SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFdSize); + SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress); + SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize); SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack) SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize); SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2)); diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S index ffa4a46..d61a15b 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S @@ -35,8 +35,8 @@ ASM_PFX(_ModuleEntryPoint): _SetupStack: # Setup Stack for the 4 CPU cores - LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase) ,r1) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize) ,r2) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase), r1) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize), r2) mov r3,r0 @ r3 = core_id mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base @@ -55,7 +55,7 @@ _AllocateGlobalPeiVariables: _PrepareArguments: # The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector - LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2) + LoadConstantToReg (FixedPcdGet32(PcdNormalFvBaseAddress), r2) add r2, r2, #4 ldr r1, [r2] diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm index 231c14e..e214ed3 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm @@ -53,7 +53,7 @@ _AllocateGlobalPeiVariables _PrepareArguments // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector - LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2) + LoadConstantToReg (FixedPcdGet32(PcdNormalFvBaseAddress), r2) add r2, r2, #4 ldr r1, [r2] diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf index 4ca81f5..917da5d 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf @@ -53,8 +53,8 @@ gArmPlatformTokenSpaceGuid.PcdStandalone [FixedPcd] - gArmTokenSpaceGuid.PcdNormalFdBaseAddress - gArmTokenSpaceGuid.PcdNormalFdSize + gArmTokenSpaceGuid.PcdNormalFvBaseAddress + gArmTokenSpaceGuid.PcdNormalFvSize gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf index c14e735..aeaa0db 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf @@ -42,7 +42,6 @@ IoLib ArmLib ArmPlatformLib - SerialPortLib [Ppis] gEfiTemporaryRamSupportPpiGuid @@ -51,8 +50,8 @@ gArmPlatformTokenSpaceGuid.PcdStandalone [FixedPcd] - gArmTokenSpaceGuid.PcdNormalFdBaseAddress - gArmTokenSpaceGuid.PcdNormalFdSize + gArmTokenSpaceGuid.PcdNormalFvBaseAddress + gArmTokenSpaceGuid.PcdNormalFvSize gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c index b8e5225..64cf0f0 100644 --- a/ArmPlatformPkg/Sec/Sec.c +++ b/ArmPlatformPkg/Sec/Sec.c @@ -121,18 +121,18 @@ CEntryPoint ( // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM if (FeaturePcdGet(PcdSkipPeiCore) || !FeaturePcdGet(PcdStandalone)) { // Initialize system memory (DRAM) - ArmPlatformInitializeSystemMemory(); + ArmPlatformInitializeSystemMemory (); } // Some platform can change their physical memory mapping - ArmPlatformBootRemapping(); + ArmPlatformBootRemapping (); } // Test if Trustzone is supported on this platform if (ArmPlatformTrustzoneSupported()) { if (FixedPcdGet32(PcdMPCoreSupport)) { // Setup SMP in Non Secure world - ArmSetupSmpNonSecure(CoreId); + ArmSetupSmpNonSecure (CoreId); } // Enter Monitor Mode @@ -206,7 +206,7 @@ CEntryPoint ( // If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address if (FeaturePcdGet(PcdStandalone) == FALSE) { if (CoreId == ARM_PRIMARY_CORE) { - UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFdBaseAddress); + UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress); // Patch the DRAM to make an infinite loop at the start address *StartAddress = 0xEAFFFFFE; // opcode for while(1) @@ -215,7 +215,7 @@ CEntryPoint ( SerialPortWrite ((UINT8 *) Buffer, CharCount); // To enter into Non Secure state, we need to make a return from exception - return_from_exception(PcdGet32(PcdNormalFdBaseAddress)); + return_from_exception(PcdGet32(PcdNormalFvBaseAddress)); } else { // When the primary core is stopped by the hardware debugger to copy the firmware // into DRAM. The secondary cores are still running. As soon as the first bytes of @@ -229,7 +229,7 @@ CEntryPoint ( } } else { // To enter into Non Secure state, we need to make a return from exception - return_from_exception(PcdGet32(PcdNormalFdBaseAddress)); + return_from_exception(PcdGet32(PcdNormalFvBaseAddress)); } //-------------------- Non Secure Mode --------------------- @@ -247,7 +247,7 @@ NonSecureWaitForFirmware ( VOID (*secondary_start)(VOID); // The secondary cores will execute the firmware once wake from WFI. - secondary_start = (VOID (*)())PcdGet32(PcdNormalFdBaseAddress); + secondary_start = (VOID (*)())PcdGet32(PcdNormalFvBaseAddress); ArmCallWFI(); diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf index 38bd8b9..d36fc0c 100644 --- a/ArmPlatformPkg/Sec/Sec.inf +++ b/ArmPlatformPkg/Sec/Sec.inf @@ -52,7 +52,7 @@ gArmTokenSpaceGuid.PcdVFPEnabled gArmPlatformTokenSpaceGuid.PcdMPCoreSupport - gArmTokenSpaceGuid.PcdNormalFdBaseAddress + gArmTokenSpaceGuid.PcdNormalFvBaseAddress gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize -- cgit v1.1