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2019-08-21UefiCpuPkg: Adding a new TSC library by using CPUID(0x15) TSC leafDonald Kuo13-0/+643
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1909 Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Signed-off-by: Donald Kuo <donald.kuo@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-08-21UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.Dong, Eric4-132/+61
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 Below code is current implementation: if (MsrRegister[ProcessorNumber].Bits.Lock == 0) { CPU_REGISTER_TABLE_WRITE_FIELD ( ProcessorNumber, Msr, MSR_IA32_FEATURE_CONTROL, MSR_IA32_FEATURE_CONTROL_REGISTER, Bits.Lock, 1 ); } 1. In first normal boot, the Bits.Lock is 0, 1 will be added into the register table and then will set to the MSR. 2. Trig warm reboot, MSR value preserves. After normal boot phase, the Bits.Lock is 1, so it will not be added into the register table during the warm reboot phase. 3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is not added in register table, so it's still 0 after resume. This is not an expect behavior. The expect value is the value should always 1 after booting or resuming from S3. The root cause for this issue is 1. driver bases on current value to insert the "set value action" to the register table. 2. Some MSRs may reserve their value during warm reboot. The solution for this issue is using new added macros for the MSRs which preserve value during warm reboot. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-08-21UefiCpuPkg/RegisterCpuFeaturesLib: Supports test then write new value logic.Dong, Eric1-1/+30
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 Supports new logic which test current value before write new value. Only write new value when current value not same as new value. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-08-21UefiCpuPkg/RegisterCpuFeaturesLib: Combine CR read/write action.Dong, Eric1-47/+63
Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-08-21UefiCpuPkg/PiSmmCpuDxeSmm: Supports test then write new value logic.Dong, Eric1-0/+29
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 Supports new logic which test current value before write new value. Only write new value when current value not same as new value. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-21UefiCpuPkg/PiSmmCpuDxeSmm: Combine CR read/write action.Dong, Eric1-42/+62
Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-21UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros.Dong, Eric3-4/+134
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 Add below new micros which test the current value before write the new value. Only write new value when current value not same as new value. CPU_REGISTER_TABLE_TEST_THEN_WRITE32 CPU_REGISTER_TABLE_TEST_THEN_WRITE64 CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD Also add below API: CpuRegisterTableTestThenWrite Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Cc: Star Zeng <star.zeng@intel.com>
2019-08-21UefiCpuPkg/PiSmmCpuDxeSmm: don't free page table pages that are required to ↵Damian Nikodem1-40/+59
handle current page fault Reclaim may free page table pages that are required to handle current page fault. This causes a page leak, and, after sufficent number of specific page fault+reclaim pairs, we run out of reclaimable pages and hit: ASSERT (MinAcc != (UINT64)-1); To remedy, prevent pages essential to handling current page fault: (1) from being considered as reclaim candidates (first reclaim phase) (2) from being freed as part of "branch cleanup" (second reclaim phase) Signed-off-by: Damian Nikodem <damian.nikodem@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Krzysztof Rusocki <krzysztof.rusocki@intel.com>
2019-08-16UefiCpuPkg/Cpuid: Add description for parameter LeafFunctionShenglei Zhang1-0/+2
LeafFunction needs to be described in comments. https://bugzilla.tianocore.org/show_bug.cgi?id=2052 Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-08-13UefiCpuPkg/PiSmmCpuDxeSmm: Fix coding styleShenglei Zhang2-6/+6
1. Update CPUStatus to CpuStatus in comments to align comments with code. 2. Add "OUT" attribute for "ProcedureArguments" parameter in function header. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-08-09UefiCpuPkg/PiSmmCpuDxeSmm: Clean up useless ConsoleLogLock spinlock.Eric Dong1-2/+0
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2060 Remove the useless ConsoleLogLock spinlock. Signed-off-by: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-09UefiCpuPkg/RegisterCpuFeaturesLib: Clean up useless ConsoleLogLock spinlock.Eric Dong2-2/+0
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2060 Remove the useless ConsoleLogLock spinlock. Signed-off-by: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-09UefiCpuPkg: Update code to include register definitions from MdePkgNi, Ray16-37/+35
Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09UefiCpuPkg|MdePkg: Move Register/ folder to MdePkg/Include/Ni, Ray33-53504/+19
The patch moves all files under UefiCpuPkg/Include/Register/ to MdePkg/Include/Register using following detailed approaches: 1. Move UefiCpuPkg/Include/Register/Amd/ to MdePkg/Include/Register/Amd folder. 2. Move remaining in UefiCpuPkg/Include/Register/ to MdePkg/Include/Register/Intel folder. 3. Create wrapper header files under UefiCpuPkg/Include/Register/ to include the accordingly files in MdePkg/Include/Register/Intel. This is to avoid build break because code in other repos like edk2-platform includes the file from UefiCpuPkg. The wrapper header files will be removed after all consumers code is updated. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09MdePkg/Cpuid.h: Move Cpuid.h from UefiCpuPkg to MdePkgNi, Ray1-3981/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 MdeModulePkg/DxeIpl needs to get CPUID output for CPU 5-level paging capability detection. In order to use the macros/structures defined in UefiCpuPkg/Include/Register/Cpuid.h, the patch adds Intel/Cpuid.h to MdePkg/Include/Register/ directory and updates Cpuid.h in UefiCpuPkg to include the new one in MdePkg. Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09UefiCpuPkg/CpuDxe: Support parsing 5-level page tableNi, Ray2-2/+19
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09UefiCpuPkg/CpuDxe: Remove unnecessary macrosNi, Ray1-19/+24
Today's code defines macros like CR0_PG, CR0_WP, CR4_PSE, CR4_PAE when checking whether individual bits are set in CR0 or CR4 register. The patch changes the code to use IA32_CR0 and IA32_CR4 structure defined in MdePkg/Include/Library/BaseLib.h so that the module local macros can be removed. There is no functionality impact to this change. Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabledNi, Ray4-2/+32
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 MpInitLib is the library that's responsible to wake up APs to provide MP PPI and Protocol services. The patch synchronizes BSP's CR4.LA57 to each AP's CR4.LA57. Without this change, AP may enter to GP fault when BSP's 5-level page table is set to AP during AP wakes up. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-06UefiCpuPkg/PiSmmCpuDxeSmm: Remove debug message.Eric Dong1-21/+1
This debug message may be called by BSP and APs. It may caused ASSERT when APs call this debug code. In order to avoid system boot assert, Remove this debug message. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com>
2019-08-06UefiCpuPkg/RegisterCpuFeaturesLib: Remove debug message.Eric Dong1-22/+0
This debug message may be called by BSP and APs. It may caused ASSERT when APs call this debug code. In order to avoid system boot assert, Remove this debug message. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com>
2019-08-06UefiCpuPkg/PiSmmCpuDxeSmm: Make code consistent with commentsshenglei2-3/+3
1.Remove "out" attribute for " Buffer" parameter in function header. 2.Add "out" attribute for " Token" parameter in function header. 3.Update ProcedureArgument to ProcedureArguments. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-08-05UefiCpuPkg/PiSmmCpuDxeSmm: Add check for pointer Pml5EntryShenglei Zhang1-0/+1
The pointer Pml5Entry, returned from call to function AllocatePageTableMemory, may be null. So add check for it. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-08-02UefiCpuPkg/MpInitLib: don't shadow the microcode patch twice.Eric Dong1-29/+33
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1982 MpInitLibInitialize in MpLib.c will be invoked on both PEI and DXE CPU code, MicrocodeDetect would be performed twice and copy Microcode from flash to memory twice as well, which consider as duplicate work to lead longer boot time. This patch just use microcode memory copied in PEI phase if exist. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-02UefiCpuPkg/PiSmmCpuDxeSmm: Keep function comment and declaration adjacentShenglei Zhang1-1/+0
Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-07-29UefiCpuPkg/RegisterCpuFeaturesLib: Start all processors simultaneously.Eric Dong5-23/+53
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 For semaphore type register, it required all processors to do the task at the same time. Current logic begins BSP's task after all APs have finished their tasks. This will caused set semaphore task hang if semaphore has package level type. This patch use new EDKII_PEI_MP_SERVICES2_PPI to start all processors at the same time to fix the potential hang issue. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-07-29UefiCpuPkg/CpuMpPei: Produce EDKII_PEI_MP_SERVICES2_PPI.Eric Dong4-7/+436
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 Produce new EDKII_PEI_MP_SERVICES2_PPI service. It includes all APIs existed in EFI_PEI_MP_SERVICES_PPI and add new API EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2019-07-29UefiCpuPkg: Add new EDKII_PEI_MP_SERVICES2_PPIEric Dong2-0/+282
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 Add definition for new EDKII_PEI_MP_SERVICES2_PPI. It includes all APIs existed in EFI_PEI_MP_SERVICES_PPI and add new API EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2019-07-29UefiCpuPkg/MpInitLibUp: Add MpInitLibStartupAllCPUs API.Eric Dong1-0/+35
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 Add new MpInitLibStartupAllCPUs API uses to start all processors at the same time. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-07-29UefiCpuPkg/MpInitLib: Add MpInitLibStartupAllCPUs API.Eric Dong4-10/+67
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 Add new MpInitLibStartupAllCPUs API uses to start all processors at the same time. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2019-07-29UefiCpuPkg/Include/MpInitLib.h: Add MpInitLibStartupAllCPUs API.Eric Dong1-1/+35
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 Add new MpInitLibStartupAllCPUs API uses to start all processors at the same time. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2019-07-26Revert "UefiCpuPkg/PiSmmCpu: Allow SMM access-out when static paging is OFF"Laszlo Ersek1-15/+6
This reverts commit 30f6148546c7092650ab4886fc6d95d5065c3188. Commit 30f6148546c7 causes a build failure, when building for IA32: > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c: In function > 'PerformRemainingTasks': > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c:1440:9: error: > 'mCpuSmmStaticPageTable' undeclared (first use in this function) > if (mCpuSmmStaticPageTable) { "mCpuSmmStaticPageTable" is an X64-only variable. It is defined in "X64/PageTbl.c", which is not linked into the IA32 binary. We must not reference the variable in such code that is linked into both IA32 and X64 builds, such as "PiSmmCpuDxeSmm.c". We have encountered the same challenge at least once in the past: - https://bugzilla.tianocore.org/show_bug.cgi?id=1593 - commit 37f9fea5b88d ("UefiCpuPkg\CpuSmm: Save & restore CR2 on-demand paging in SMM", 2019-04-04) The right approach is to declare a new function in "PiSmmCpuDxeSmm.h", and to provide two definitions for the function, one in "Ia32/PageTbl.c", and another in "X64/PageTbl.c". The IA32 implementation should return a constant value. The X64 implementation should return "mCpuSmmStaticPageTable". (In the example named above, the functions were SaveCr2() and RestoreCr2().) Signed-off-by: Laszlo Ersek <lersek@redhat.com> [lersek@redhat.com: push revert immediately, due to build breakage that would have been easy to catch before submitting the patch]
2019-07-26UefiCpuPkg/PiSmmCpu: Allow SMM access-out when static paging is OFFNi, Ray1-6/+15
Commit c60d36b4d1ee1f69b7cca897d3621dfa951895c2 * UefiCpuPkg/SmmCpu: Block access-out only when static paging is used updated page fault handler to treat SMM access-out as allowed address when static paging is not used. But that commit is not complete because the page table is still updated in SetUefiMemMapAttributes() for non-SMRAM memory. When SMM code accesses non-SMRAM memory, page fault is still generated. This patch skips to update page table for non-SMRAM memory and page table itself. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-07-18UefiCpuPkg/RegisterCpuFeaturesLib: avoid use dynamic PCD.Dong, Eric3-102/+79
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1972 Function in this library may be used by APs. Assert will be trig if AP uses dynamic pcd. This patch enhance the current code, remove the unnecessary usage of dynamic PCD. This change try to avoid report this issue again later. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2019-07-18UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiServices table.Eric Dong2-5/+13
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1972 AP calls CollectProcessorData() to collect processor info. CollectProcessorData function finally calls PcdGetSize function to get DynamicPCD PcdCpuFeaturesSetting value. PcdGetSize will use PeiServices table which caused below assert info: Processor Info: Package: 1, MaxCore : 4, MaxThread: 1 Package: 0, Valid Core : 4 ASSERT [CpuFeaturesPei] c:\projects\jsl\jsl_v1193\Edk2\MdePkg\Library \PeiServicesTablePointerLibIdt\PeiServicesTablePointer.c(48): PeiServices != ((void *) 0) This change uses saved global pcd size instead of calls PcdGetSize to fix this issue. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2019-07-18UefiCpuPkg DxeRegisterCpuFeaturesLib: Fix VS2012 build failureStar Zeng1-0/+6
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1968 The new VS2012 build failure is caused by 7a0df26. xxx\registercpufeatureslib\dxeregistercpufeatureslib.c(258) : warning C4701: potentially uninitialized local variable 'MpEvent' used It is a false positive alarm. MpEvent is assigned at line 238 and will be used at line 258, both lines are controlled by "if (CpuFeaturesData->NumberOfCpus > 1)". This patch initializes MpEvent to suppress incorrect compiler/analyzer warnings. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-07-16UefiCpuPkg CpuCommonFeaturesLib: Enhance Ppin codeStar Zeng3-12/+72
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1961 Enhance Ppin code to enable and unlock for TRUE State, and disable and lock for FALSE State. Note: enable and lock could not be set both. According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP, and writing 1 to LockOut is permitted only if Enable_PPIN is clear. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-07-16UefiCpuPkg/PiSmmCpuDxeSmm: Enable MM MP ProtocolEric Dong6-25/+1391
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1937 Add MM Mp Protocol in PiSmmCpuDxeSmm driver. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2019-07-12UefiCpuPkg/PiSmmCpu: ReclaimPages: fix incorrect operator bindingRay Ni1-1/+1
Fixes: 4eee0cc7c Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-07-12UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supportsRay Ni5-300/+561
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1946 The patch changes SMM environment to use 5 level paging when CPU supports it. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> (cherry picked from commit 7365eb2c8cf1d7112330d09918c0c67e8d0b827a)
2019-07-12Revert "UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports"Ray Ni5-561/+300
This reverts commit 7365eb2c8cf1d7112330d09918c0c67e8d0b827a. Commit 7c5010c7f8 MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging technically breaks the EDKII development process documented in https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process and Maintainers.txt in EDKII repo root directory. The voilation is commit 7c5010c7f8 doesn't have a Reviewed-by or Acked-by from MdePkg maintainers. In order to revert 7c5010c7f8, 7365eb2c8 needs to revert first otherwise simply reverting 7c5010c7f8 will cause build break. Signed-off-by: Ray Ni <ray.ni@intel.com>
2019-07-11UefiCpuPkg RegisterCpuFeaturesLib: Fix an ASSERTION issueStar Zeng3-27/+37
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1968 We met assertion like below, it happens when there is only one processor. ASSERT_EFI_ERROR (Status = Not started) ASSERT [CpuFeaturesDxe] X:\XXX\XXX\RegisterCpuFeaturesLib\ DxeRegisterCpuFeaturesLib.c(149): !EFI_ERROR (Status) The code should not call StartupAllAPs when there is only one processor. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-07-10UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supportsRay Ni5-300/+561
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1946 The patch changes SMM environment to use 5 level paging when CPU supports it. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-07-10UefiCpuPkg/PiSmmCpu: Change variable names and comments to follow SDMRay Ni1-57/+57
Per SDM, for IA-32e 4-KByte paging, there are four layers in the page table structure: 1. PML4 2. Page-Directory-Pointer Table (PDPT) 3. Page-Directory (PD) 4. Page Table (PT) The patch changes the local variable names and comments to use "PML4", "PDPT", "PD", "PT" to better align to terms used in SDM. There is no functionality impact for this change. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-06-27UefiCpuPkg/MpInitLib: MicrocodeDetect: Ensure checked range is validZhichao Gao1-3/+9
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1934 0x0 MicrocodeBegin MicrocodeEntry MicrocodeEnd 0xffffffff |--------------|---------------|---------------|---------------| valid TotalSize TotalSize is only valid between 0 and (MicrocodeEnd - MicrocodeEntry). So add '(UINTN)MicrocodeEntryPoint > (MAX_ADDRESS - TotalSize)' before '((UINTN)MicrocodeEntryPoint + TotalSize) > MicrocodeEnd' to make sure ((UINTN)MicrocodeEntryPoint + TotalSize) wouldn't overflow. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-06-13UefiCpuPkg RegisterCpuFeaturesLib.h: Fix typo 'STRICK' to 'STRIKE'Star Zeng1-1/+1
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1642 This patch fixes typo in CPU_FEATURE_THREE_STRICK_COUNTER. CPU_FEATURE_THREE_STRICK_COUNTER -> CPU_FEATURE_THREE_STRIKE_COUNTER Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-06-10UefiCpuPkg/MpInitLib: Decrease NumApsExecuting only for ApInitConfigRay Ni1-2/+3
The patch fixes the bug that the memory under 1MB is modified by firmware in S3 boot. Root cause is a racing condition in MpInitLib: 1. BSP: WakeUpByInitSipiSipi is set by NotifyOnS3SmmInitDonePpi() 2. BSP: WakeUpAP() wakes all APs to run certain procedure. 2.1. AllocateResetVector() uses <1MB memory for wake up vector. 2.1. FillExchangeInfoData() resets NumApsExecuting to 0. 2.2. WaitApWakeup() waits AP to clear WAKEUP_AP_SIGNAL. 3. AP: ApWakeupFunction() clears WAKEUP_AP_SIGNAL to inform BSP. 5. BSP: FreeResetVector() restores the <1MB memory 4. AP: ApWakeupFunction() calls the certain procedure. 4.1. NumApsExecuting is decreased. #4.1 happens after the 1MB memory is restored so the result is memory below 1MB is changed by #4.1 It happens only when the AP executes procedure a bit longer. AP returns back to ApWakeupFunction() from procedure after BSP restores the <1MB memory. Since NumApsExecuting is only used when InitFlag == ApInitConfig for counting the processor count. The patch moves the NumApsExecuting decrease to the path when InitFlag == ApInitConfig. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Nandagopal Sathyanarayanan <nandagopal.sathyanarayanan@intel.com>
2019-06-10UefiCpuPkg/MpInitLib: increase NumApsExecuting only for ApInitConfigRay Ni1-7/+7
NumApsExecuting is only used when InitFlag == ApInitConfig for counting the processor count. The patch changes Ia32 version of waking up vector assembly code to align to x64 version of waking up vector assembly code. After the change both versions of waking up vector increase NumApsExecuting when InitFlag == ApInitConfig. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-06-06UefiCpuPkg CpuCommFeaturesLib: Reduce to set MSR_IA32_CLOCK_MODULATIONStar Zeng3-26/+78
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1810 This patch covers two problems. 1. Current code gets CPUID_THERMAL_POWER_MANAGEMENT in ClockModulationInitialize() and uses its ECMD bit for all processors. But ClockModulationInitialize() is only executed by BSP, that means the bit is just for BSP. It may have no functionality issue as all processors may have same bit value in a great possibility. But for good practice, the code should get CPUID_THERMAL_POWER_MANAGEMENT in ClockModulationSupport (executed by all processors), and then use them in ClockModulationInitialize() for all processors. We can see that Aesni.c (and others) have used this good practice. 2. Current code uses 3 CPU_REGISTER_TABLE_WRITE_FIELD for MSR_IA32_CLOCK_MODULATION in ClockModulationInitialize(), they can be reduced to 1 CPU_REGISTER_TABLE_WRITE64 by getting MSR_IA32_CLOCK_MODULATION for all processors in ClockModulationSupport() and then update fields for register table write in ClockModulationInitialize(). We may argue that there may be more times of MSR_IA32_CLOCK_MODULATION getting. But actually the times of MSR_IA32_CLOCK_MODULATION getting could be also reduced. The reason is in ProgramProcessorRegister() of CpuFeaturesInitialize.c, AsmMsrBitFieldWrite64 (AsmReadMsr64 + AsmWriteMsr64) will be used for CPU_REGISTER_TABLE_WRITE_FIELD, and AsmWriteMsr64 will be used for CPU_REGISTER_TABLE_WRITE64. The times of MSR accessing could be reduced with this patch. Without the patch: 3 CPU_REGISTER_TABLE_WRITE_FIELD (in ClockModulationInitialize) ==> 3 AsmMsrBitFieldWrite64 ==> 3 AsmReadMsr64 + 3 AsmWriteMsr64 With the patch: 1 AsmReadMsr64 (in ClockModulationSupport) + 1 CPU_REGISTER_TABLE_WRITE64 (in ClockModulationInitialize) ==> 1 AsmWriteMsr64 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-06-06UefiCpuPkg CpuCommFeaturesLib: Fix ASSERT if LMCE is supportedStar Zeng2-2/+2
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1829 There will be ASSERT if LMCE is supported as below. DXE_ASSERT!: [CpuFeaturesDxe] XXX\UefiCpuPkg\Library\CpuCommonFeaturesLib\MachineCheck.c (342): ConfigData != ((void *) 0) The code should get Config Data and FeatureControlGetConfigData could be used. This issue is there since the code was added at the commit below. Revision: 3d6275c1137c9633ce24e31522b71105367bd6a0 Date: 2017/8/4 8:46:41 UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature. The commits below are also related to move the code. Revision: 023387144299741d727521b425ef443438aecc1f Date: 2017/9/1 10:12:38 UefiCpuPkg/Lmce.c Remove useless file. Revision: 306a5bcc6b0170d28b0db10bd359817bb4b1db9f Date: 2017/8/17 11:40:38 UefiCpuPkg/CpuCommonFeaturesLib: Merge machine check code to same file. So, the code may not be tested at all on a platform that supports LMCE. BTW: A typo in LmceInitialize is also fixed. The typo is introduced by the commit below. Revision: d28daaddb3e732468e930a809d3d3943a5de9558 Date: 2018/10/17 9:24:05 UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-06-06UefiCpuPkg CpuCommFeaturesLib: Fix GP fault issue about ProcTraceStar Zeng1-32/+30
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1808 In current code, the values of TopaEntryPtr->Uint64 for TopaTable and the values of OutputBaseReg.Uint64 and OutputMaskPtrsReg.Uint64 to register table write for RTIT_OUTPUT_BASE and RTIT_OUTPUT_MASK_PTRS are not been initialized in whole. For example, the reserved bits in OutputBaseReg.Uint64 are random that will cause GP fault like below when SetProcessorRegister (in CpuFeaturesInitialize.c) sets register based on register table. !!!! X64 Exception Type - 0D(#GP - General Protection) CPU Apic ID - 00000000 !!!! ExceptionData - 0000000000000000 RIP -0000000064D69576, CS -0000000000000038, RFLAGS -0000000000010246 RAX -000000006B9F1001, RCX -0000000000000560, RDX -0000000000000000 RBX -0000000064EECA18, RSP -000000006CB82BA0, RBP -0000000000000008 RSI -0000000080000000, RDI -0000000000000011 R8 -000000006B9493D0, R9 -0000000000000010, R10 -00000000000000FF R11 -000000006CB82A50, R12 -0000000064D70F50, R13 -0000000066547050 R14 -0000000064E3E198, R15 -0000000000000000 DS -0000000000000030, ES -0000000000000030, FS -0000000000000030 GS -0000000000000030, SS -0000000000000030 CR0 -0000000080010013, CR2 -0000000000000000, CR3 -000000006C601000 CR4 -0000000000000628, CR8 -0000000000000000 DR0 -0000000000000000, DR1 -0000000000000000, DR2 -0000000000000000 DR3 -0000000000000000, DR6 -00000000FFFF0FF0, DR7 -0000000000000400 GDTR -000000006B8CCF18 0000000000000047, LDTR -0000000000000000 IDTR -000000006687E018 0000000000000FFF, TR -0000000000000000 FXSAVE_STATE -000000006CB82800 And current code gets MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_OUTPUT_BASE and MSR_IA32_RTIT_OUTPUT_MASK_PTRS in ProcTraceInitialize() and uses their values for all processors. But ProcTraceInitialize() is only executed by BSP, that means the values just for BSP. For good practice, the code should get MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_OUTPUT_BASE and MSR_IA32_RTIT_OUTPUT_MASK_PTRS in ProcTraceSupport (executed by all processors), and then use them in ProcTraceInitialize() for all processors. This can also resolve the issue that the values of OutputBaseReg.Uint64 and OutputMaskPtrsReg.Uint64 are not been initialized in whole. For TopaEntryPtr->Uint64, this patch updates code to initialize it in whole explicitly by TopaEntryPtr->Uint64 = 0 before updating its fields. At the same time, this patch also eliminates the ProcTraceSupported field in PROC_TRACE_PROCESSOR_DATA and the TopaMemArrayCount field in PROC_TRACE_DATA. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
generated by cgit v1.1 at 2024-11-04 18:22:37 +0000