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2022-07-14UefiCpuPkg: Update SEC_IDT_TABLE structKuo, Ted2-2/+3
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957 The reserved IDT table size in SecCore is too small for X64. Changed the type of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have sufficient size reserved in IdtTable for X64. dff Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2022-07-08UefiCpuPkg/SecCore: Add debug messages to illuminate data flowOram, Isaac W1-0/+37
Add debug messages to make it easier to verify PlatformSecLib is passing the data properly. Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
2022-05-06UefiCpuPkg: Add CpuLib to module INFs that depend on UefiCpuLib.Yu Pu3-0/+3
There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib and UefiCpuPkg/UefiCpuLib will be merged to MdePkg/CpuLib. To avoid build failure, add CpuLib dependency to all modules that depend on UefiCpuLib. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-12-07UefiCpuPkg: Apply uncrustify changesMichael Kubacki4-153/+159
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiCpuPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-09-18UefiCpuPkg: SecCoreNative without ResetVectorS, Ashraf Ali1-0/+80
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3492 Currently SecCore.inf having the resetvector code under IA32. if the user wants to use both SecCore and UefiCpuPkg ResetVector it's not possible, since SecCore and ResetVector(VTF0.INF/ResetVector.inf) are sharing the same GUID which is BFV. to overcome this issue we can create the Duplicate version of the SecCore.inf as SecCoreNative.inf which contains pure SecCore Native functionality without resetvector. SecCoreNative.inf should have the Unique GUID so that it can be used along with UefiCpuPkg ResetVector in there implementation. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Cc: Digant H Solanki <digant.h.solanki@intel.com> Cc: Sangeetha V <sangeetha.v@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
2021-02-04UefiCpuPkg: Move MigrateGdt from DiscoverMemory to TempRamDone. (CVE-2019-11098)Guomin Jiang2-0/+46
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1614 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3160 The GDT still in flash with commit 60b12e69fb1c8c7180fdda92f008248b9ec83db1 after TempRamDone So move the action to TempRamDone event to avoid reading GDT from flash. Signed-off-by: Guomin Jiang <guomin.jiang@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2020-07-28UefiCpuPkg/SecMigrationPei: Add initial PEIM (CVE-2019-11098)Michael Kubacki3-2/+27
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1614 Adds a PEIM that republishes structures produced in SEC. This is done because SEC modules may not be shadowed in some platforms due to space constraints or special alignment requirements. The SecMigrationPei module locates interfaces that may be published in SEC and reinstalls the interface with permanent memory addresses. This is important if pre-memory address access is forbidden after memory initialization and data such as a PPI descriptor, PPI GUID, or PPI inteface reside in pre-memory. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2020-06-23UefiCpuPkg/SecCore: Add pre-memory AP vectorCole, Deric1-7/+24
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2776 Add a vector at 0xFF000 (0xFFFFF000) that can be used by Init-SIPI-SIPI to start an AP before memory is initialized. This vector jumps into the same SEC entry point as the ordinary reset vector, with a special value of "AP" in the DI register. The platform-specific SEC code is expected to check for that value and take a different path for APs, if this feature is supported by the platform. Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Deric Cole <deric.cole@intel.com>
2019-09-05UefiCpuPkg: support single EFI_PEI_CORE_FV_LOCATION_PPI in PpiListChasel Chiu1-5/+4
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2153 Current logic will skip searching EFI_PEI_CORE_FV_LOCATION_PPI when the PPI in PpiList having EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST flag, but platform may pass single PPI in PpiList that should be supported. Changed the logic to verify PpiList first before checking EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST flag. Test: Verified both single EFI_PEI_CORE_FV_LOCATION_PPI and multiple PPIs in PpiList cases and both can boot with the PeiCore specified by EFI_PEI_CORE_FV_LOCATION_PPI. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2019-08-30UefiCpuPkg/SecCore: get AllSecPpiList after SecPlatformMain.Eric Dong1-1/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2136 SecPlatformMain is a platform hook function which let platform does some update. Some platform may adjust SecCoreData->PeiTemporaryRamBase which caused former saved AllSecPpiList variable invalid. This patch update the logic to get AllSecPpiList after SecPlatformMain. If SecPlatformMain() returns no platform-specific PPI list, then there is nothing to merge, so we don't need "AllSecPpiList" at all. Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-04-09UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney8-56/+8
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-02-20UefiCpuPkg/SecCore: Wrong Debug Information for SecCoreChasel, Chiu3-36/+54
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1533 When SecCore and PeiCore in different FV, current implementation still assuming SecCore and PeiCore are in the same FV. To fix this issue 2 FVs will be input parameters for FindAndReportEntryPoints () and SecCore and PeiCore will be found in each FV and correct debug information will be reported. Test: Booted with internal platform successfully. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-02-15UefiCpuPkg/SecCore: Support EFI_PEI_CORE_FV_LOCATION_PPIChasel, Chiu1-4/+4
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524 Previous commit 373c2c5b888d029d7103206556bb85f33d980569, missed one comment change that should be fixed. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2019-02-15UefiCpuPkg/SecCore: Support EFI_PEI_CORE_FV_LOCATION_PPIChasel, Chiu3-8/+33
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524 EFI_PEI_CORE_FV_LOCATION_PPI may be passed by platform when PeiCore not in BFV so SecCore has to search PeiCore either from the FV location provided by EFI_PEI_CORE_FV_LOCATION_PPI or from BFV. Test: Verified on internal platform and booting successfully. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-09-26UefiCpuPkg SecCore:Add a GUID removed previouslyZhang, Shenglei1-0/+3
The Guid gPeiSecPerformancePpiGuid removed previously is added into SecCore.inf. https://bugzilla.tianocore.org/show_bug.cgi?id=1203 Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2018-09-21UefiCpuPkg: Remove redundant library classes, Ppis and GUIDsshenglei3-8/+0
Some redundant library classes Ppis and GUIDs have been removed in inf, .c and .h files. v2: 1.Remove ReadOnlyVariable2.h in S3Resume.c which should be deleted in last version in which gEfiPeiReadOnlyVariable2PpiGuid was removed. 2.Remove the library class BaseLib in CpuPageTable.c which is included elsewhere. 3.Add library classes in SecCore.inf which are removed at last version. They are DebugAgentLib and CpuExceptionHandlerLib. 4.Add two Ppis in SecCore.inf which are removed at last version. They are gEfiSecPlatformInformationPpiGuid and gEfiSecPlatformInformation2PpiGuid. https://bugzilla.tianocore.org/show_bug.cgi?id=1043 https://bugzilla.tianocore.org/show_bug.cgi?id=1013 https://bugzilla.tianocore.org/show_bug.cgi?id=1032 https://bugzilla.tianocore.org/show_bug.cgi?id=1016 Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2018-06-29UefiCpuPkg: Removing ipf which is no longer supported from edk2.chenc21-2/+2
Removing rules for Ipf sources file: * Remove the source file which path with "ipf" and also listed in [Sources.IPF] section of INF file. * Remove the source file which listed in [Components.IPF] section of DSC file and not listed in any other [Components] section. * Remove the embedded Ipf code for MDE_CPU_IPF. Removing rules for Inf file: * Remove IPF from VALID_ARCHITECTURES comments. * Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section. * Remove the INF which only listed in [Components.IPF] section in DSC. * Remove statements from [BuildOptions] that provide IPF specific flags. * Remove any IPF sepcific sections. Removing rules for Dec file: * Remove [Includes.IPF] section from Dec. Removing rules for Dsc file: * Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC. * Remove any IPF specific sections. * Remove statements from [BuildOptions] that provide IPF specific flags. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2018-05-08UefiCpuPkg/SecMain: Add NORETURN decorator to SecStartup().Marvin H?user2-2/+9
The function SecStartup() is not supposed to return. Hence, add the NORETURN decorator. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2018-02-01UefiCpuPkg: Remove the unused file ResetVec.asm16Liming Gao1-106/+0
ResetVec.nasmb is used. ResetVec.asm16 can be retired. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2017-12-08UefiCpuPkg: Update SecCore to get BFV size based on BFV header FvLengthLiming Gao1-1/+1
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-08-02UefiCpuPkg SecCore: Fix operands of different size in bitwise operationStar Zeng1-1/+1
It is introduced by 9e9ca2100f22be29f1a53129d741f4305ff34a71. Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2017-08-01UefiCpuPkg SecCore: Add SecPerformancePpiCallBackStar Zeng3-1/+77
Add SecPerformancePpiCallBack to get SEC performance data and build HOB to convey the SEC performance data to DXE phase. Cc: Liming Gao <liming.gao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2017-08-01UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to be 8byte alignedStar Zeng1-1/+7
As HOB which has 8byte aligned requirement will be built based on them in PEI phase. Cc: Liming Gao <liming.gao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-12-14UefiCpuPkg: Make the comments align with the functionsDandan Bi1-8/+8
Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-18UefiCpuPkg/SecCore: Correct print format for stack informationJeff Fan1-2/+2
v2: Per Laszlo and Andrew's comments at https://lists.01.org/pipermail/edk2-devel/2016-November/004759.html SecCoreData->StackBase is VOID * type. We should use %p to dump VOID * type. SecCoreData->StackSize is UINTN type, but %x only could print unsinged-int type. We will cast it to UINT32 firstly and then use %x to print it. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Andrew Fish <afish@apple.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-11-09UefiCpuPkg: Display new stack base and sizeJeff Fan1-1/+9
Dump new stack base and size information could help developer to narrow down stack crash issue. Cc: Feng Tian <feng.tian@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-21UefiCpuPkg/SecCore: SecPlatformInformation(2) are optional PPIsJeff Fan1-0/+2
Currently, this is ASSERT() if neither SecPlatformInformation2 nor SecPlatformInformation PPIs are found. This is not correct. Per PI specification both of them are optional PPI. Platform may not install them. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-21UefiCpuPkg/SecCore: Fix comment typoJeff Fan1-6/+6
Revert SecPlatformInformation2 and SecPlatformInformation in two comment blocks. And correct the words. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-14UefiCpuPkg/SecCore: Re-install SEC platform information(2) PPIJeff Fan4-1/+146
In SecTemporaryRamDone(), we will build one privated GUIDed-HOB to save CPU BIST Data and re-install SEC platform information(2) PPI. Then other PEI drivers could get CPU BIST data from the private GUIDed-HOB by new installed PPI. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/SecCore: Abstract worker function GetBistFromHob()Jeff Fan1-20/+61
Abstract one worker function to get CPU BIST from the GUIDed-HOB. Add SecPlatformInformationBist() and SecPlatformInformation2Bist() to invoke GetBistFromHob(). Add in/out for parameter in function header. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/SecCore: Add SecBist.cJeff Fan3-2/+149
Add SecBist.c and copy GetBistInfoFromPpi() and SecPlatformInformation2() from UefiCpuPkg/CpuMpPei/CpuBist.c. And update SecMain.c, SecMain.inf and UefiCpuPkg.dsc accordinlgy to pass build. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-07-11UefiCpuPkg SecCore: Update SecCore inf to refer to nasmb sourceLiming Gao1-4/+2
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-06-22UefiCpuPkg/SecMain: Decorate phase-transition function with NORETURN.Marvin H?user1-1/+3
This patch adds the NORETURN attribute to the function that transfers to the PEI phase, along with an UNREACHABLE() call at the end to avoid false warnings. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2015-12-15UefiCpuPkg: Convert all .uni files to utf-8Jordan Justen2-0/+0
To convert these files I ran: $ python3 BaseTools/Scripts/ConvertUni.py UefiCpuPkg Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19264 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-19UefiCpuPkg: Add SecCore moduleMichael Kinney8-0/+883
Add SecCore module that uses the PlatformSecLib class for platform specific actions. The SecCore module also uses a new PCD to configure the size of the stack used in the SEC phase. If the stack size PCD is set to 0, the stack is configured to use half of the available temporary RAM. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18636 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.1 at 2024-08-25 12:19:55 +0000