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2020-09-16IntelFsp2WrapperPkg： remove gPeiTpmInitializationDonePpiGuid from DepexQi Zhang2-4/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2963 Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Qi Zhang <qi1.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2020-09-01IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec: add FspMeasurementLib.hQi Zhang1-0/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2944 Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Eric Dong <eric.dong@intel.com> Signed-off-by: Qi Zhang <qi1.zhang@intel.com> Message-Id: <20200831020721.8967-1-qi1.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2020-08-26IntelFsp2WrapperPkg/dsc: add HashLib, Tpm2CommandLib and Tpm2DeviceLibQi Zhang1-0/+4
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2376 Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Qi Zhang <qi1.zhang@intel.com> Message-Id: <20200818062618.3698-9-qi1.zhang@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2020-08-26IntelFsp2Wrapper/dsc: Add FspTpmMeasurementLib and PcdFspMeasurementConfig.Jiewen Yao2-2/+23
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2376 Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Qi Zhang <qi1.zhang@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200818062618.3698-7-qi1.zhang@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> [lersek@redhat.com: extend (C) notice in DEC to 2020 per Chasel's request] Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2020-08-26IntelFsp2WraperPkg/Fsp{m|s}WrapperPeim: Add FspBin measurement.Jiewen Yao4-19/+204
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2376 Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Qi Zhang <qi1.zhang@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200818062618.3698-5-qi1.zhang@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2020-08-26IntelFsp2WrapperPkg/FspMeasurementLib: Add BaseFspMeasurementLib.Jiewen Yao2-0/+302
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2376 Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Qi Zhang <qi1.zhang@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200818062618.3698-4-qi1.zhang@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2020-08-26IntelFsp2WrapperPkg/FspMeasurementLib: Add header file.Jiewen Yao1-0/+39
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2376 Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Qi Zhang <qi1.zhang@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200818062618.3698-3-qi1.zhang@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2020-06-23IntelFsp2WrapperPkg: Add FSP*_ARCH_UPD.Chasel Chiu1-2/+24
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781 Provides sample code to include FSPT_ARCH_UPD initial values with UPD header revision set to 2. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2019-12-11IntelFsp2WrapperPkg: Fix various typosAntoine Coeur8-13/+13
Fix various typos in comments and documentation. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2019-09-05IntelFsp2WrapperPkg: Remove unneeded MdeModulePkg dependencyRay Ni2-6/+2
Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2019-04-28IntelFsp2WrapperPkg/FspWrapperNotifyDxe: make global variable staticZhichao Gao1-2/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1740 Add a 'static' storage-class specifier to the global variables that only used in a single file to minimize the name collisions. This is only for the variable named 'mExitBootServicesEvent'. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2019-04-23IntelFsp2WrapperPkg/FspsWrapperPeim: Fix coding style.Chasel Chiu1-5/+5
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1730 Internal code quality check failed after this commit: 68d47eea422d64eeb9872b927620f579f4ccfc0f, fixed those coding style issues. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2019-04-16IntelFsp2WrapperPkg: Perform post FSP-S process.Chasel, Chiu3-18/+97
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1716 In API mode FSP wrapper will perform some post FSP-S process but such process was skipped in Dispatch mode which may impact some of the boot loaders. To align behavior between API and Dispatch, an End-of-Pei callback is introduced to perform same process in Dispatch mode. Note: If boot loader implemented its own PostFspsHobProcess (), it has to check PcdFspModeSelection and support each mode properly. Test: Verified on internal platform and both FSP API and Dispatch modes booted successfully. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2019-04-09IntelFsp2WrapperPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney39-265/+39
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-11-26IntelFsp2WrapperPkg: Fix constant if statements issueChasel, Chiu2-2/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1351 Internal code quality scanning found 2 constant if statements related to FixedPcdGet8 () usage. Since the PCD can be PatchableInModule too, it should be changed to PcdGet8 () to fix this issue. Test: Verified on internal platform and booted successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Cc: Wu Hao A <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
2018-11-26IntelFsp2WrapperPkg: Fix line ending format issueChasel, Chiu5-43/+43
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1352 Fixed line ending format wrong issues on some files. Test: Verified building successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Cc: Wu Hao A <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
2018-11-20IntelFsp2WrapperPkg: Support FSP Dispatch modeChasel, Chiu5-10/+43
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1300 Provides PCD selection for FSP Wrapper to support Dispatch mode. Also PcdFspmBaseAddress should support Dynamic for recovery scenario (multiple FSP-M binary in flash) Test: Verified on internal platform and both API and DISPATCH modes booted successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-11-20IntelFsp2WrapperPkg: Revert 90c5bc08Chasel, Chiu5-43/+10
Commit message issue and reverted commit 90c5bc081d15d077606131a61114ddfdefe62e61. Will re-submit with correct formats. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-11-20IntelFsp2WrapperPkg: Support FSP Dispatch modeChasel, Chiu5-10/+43
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1300 Provides PCD selection for FSP Wrapper to support Dispatch mode. Also PcdFspmBaseAddress should support Dynamic for recovery scenario (multiple FSP-M binary in flash) Test: Verified on internal platform and both API and DISPATCH modes booted successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-28IntelFsp2WrapperPkg/BaseFspWrapperPlatformLibSample: Remove PCDsshenglei1-3/+0
The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-28IntelFsp2WrapperPkg/FspWrapperNotifyDxe: Remove an unused PCDshenglei1-1/+0
The PCD below is unused, so it has been removed from inf. gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-28IntelFsp2(Wrapper)Pkg: Revert from e8208100 to 737f812bChasel, Chiu2-0/+4
Commit formats had issues so reverted 9 commits from IntelFsp2Pkg and IntelFsp2WrapperPkg. Will re-submit them with correct formats. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-09-27[PATCH v3 06/16] IntelFsp2WrapperPkg/BaseFspWrapperPlatformLibSample:Chasel, Chiu1-3/+0
Remove PCDs The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-27[PATCH v3 05/16] IntelFsp2WrapperPkg/FspWrapperNotifyDxe: Remove anChasel, Chiu1-1/+0
unused PCD The PCD below is unused, so it has been removed from inf. gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-08-22IntelFsp2WrapperPkg: Add EFIAPI to AsmExecute32BitCodeChasel, Chiu1-1/+2
AsmExecute32BitCode is assembly code and needs EFIAPI Cc: Jiewen Yao <Jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-06-28IntelFsp2WrapperPkg: Clean up source filesLiming Gao3-6/+6
1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
2018-01-18IntelFsp2WrapperPkg: Update BaseFspWrapperApiLib to pass XCODE5 buildLiming Gao1-5/+5
XCODE5 doesn't support absolute addressing in the assembly code. This change uses lea instruction to get the address. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-12-28IntelFspWrapperPkg: Convert INF file to dos formatLiming Gao1-1/+1
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-11-29IntelFsp2WrapperPkg: Support UPD allocation outside FspWrapperChasel, Chiu5-52/+76
UPD allocation and patching can be done outside FspWrapper as implementation choice so adding a PCD to select between original FspWrapper allocation model or outside model Cc: Jiewen Yao <Jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-10-10IntelFsp2WrapperPkg: Update Protocol/Guid usage in INF filesLiming Gao4-15/+10
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-08-03edk2: Move License.txt file to rootMichael D Kinney1-25/+0
https://bugzilla.tianocore.org/show_bug.cgi?id=642 Add top level License.txt file with the BSD 2-Clause License that is used by the majority of the EKD II open source project content. Merge copyright statements from the BSD 2-Clause License files in each package directory and remove the duplication License.txt file from package directories. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-08-03edk2: Move TianoCore Contribution Agreement to rootMichael D Kinney1-218/+0
https://bugzilla.tianocore.org/show_bug.cgi?id=629 Move Contributions.txt that contains the TianoCore Contribution Agreement 1.0 to the root of the edk2 repository and remove the duplicate Contributions.txt files from all packages. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-04-06IntelFsp2WrapperPkg: Convert files to CRLF line endingHao Wu1-7/+7
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-03-13IntelFsp2WrapperPkg: Add Readme.mdJiewen Yao1-0/+7
Cc: Maurice Ma <maurice.ma@intel.com> Cc: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-03-06IntelFsp2WrapperPkg: Refine casting expression result to bigger sizeHao Wu2-7/+7
There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c = (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c = (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c = a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c = (VOID *)(UINTN)(a + b); --> c = (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-10-28IntelFsp2WrapperPkg: Add a PCD to control if signaling PciEnumerationComplete.Dong, Guo3-8/+33
PciEnumerationComplete might be signaled to FSP in Coreboot. So FSP wrapper driver don't need send it again. Add a PCD to control if a FSP API could be skipped from FspWrapperNotifyDxe driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-10-27IntelFsp2Pkg: Added changes to enable FPDT performance measurementsYarlagadda, Satya P3-32/+33
IntelFsp2Pkg: 1.Defined performance measure mask to mask the Perf id (Bits 63:56) of the Perf Data from FSP Global data. 2.Replaced the hard coded perf ids to use the standard defines from FspStatuscode.h 3.Add the PerfData form Fsp Global data ( for TempRaminit entry, TempramInit exit, memoryinit entry) to FPDT entries IntelFsp2WrapperPkg: Moved the code to add the FSP FPDT records and wrapper FPDT records from ReadytoBoot event to EndofFirmware event Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-10-24IntelFsp2WrapperPkg: Fix a typo in the commentGary Lin1-1/+1
- boundry -> boundary Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gary Lin <glin@suse.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-08IntelFsp2WrapperPkg DSC: Add build option to disable deprecated APIsHao Wu1-0/+3
Add the following definition in the [BuildOptions] section in package DSC files to disable APIs that are deprecated: [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-07-26IntelFsp2WrapperPkg: Add missing License.txt.Jiewen Yao1-0/+25
Add missing License.txt. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-20IntelFsp2WrapperPkg: Add missing modules in Package DSCLiming Gao1-0/+7
Package DSC is used to verify the module source build. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-20IntelFsp2WrapperPkg SecFspWrapperPlatformSecLibSample:Update code to pass buildLiming Gao3-9/+10
1. Update its library class to PlatformSecLib 2. Update source code to refer to the matched header file Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14IntelFsp2WrapperPkg: Remove unused header files from Fspm and Fsps WrapperPeimLiming Gao2-2/+0
PlatformSecLib.h is not used and removed. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-11IntelFsp2WrapperPkg SecFspWrapperPlatformSecLibSample: Remove MASM/GAS filesLiming Gao7-1124/+0
Keep NASM file only for new added modules. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-11IntelFsp2WrapperPkg BaseFspWrapperApiLib: Remove MASM/GAS filesLiming Gao3-462/+0
Keep NASM file only for new added modules. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-01IntelFsp2WrapperPkg: Add error handling for possible NULL ptr dereferenceHao Wu2-0/+10
Possible NULL pointer dereference for FspmHeaderPtr/FspsHeaderPtr in module FspmWrapperPeim/FspsWrapperPeim. Add error handling codes to avoid this issue. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-06-28IntelFsp2WrapperPkg SecFspWrapperPlatformSecLibSample: Convert ASM to NASMLiming Gao4-0/+559
Manually converts Ia32/PeiCoreEntry.asm, Ia32/SecEntry.asm and Ia32/Stack.asm to Ia32/PeiCoreEntry.nasm, Ia32/SecEntry.nasm and Ia32/Stack.nasm. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28IntelFsp2WrapperPkg BaseFspWrapperApiLib: Convert X64/Thunk64To32.asm to NASMLiming Gao2-0/+231
Manually convert X64/Thunk64To32.asm to X64/Thunk64To32.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-18IntelFsp2WrapperPkg: Add support to handle ResetRequired return Status from FSP.Jiewen Yao6-1/+105
As per FSP 2.0 spec, FSP shall not trigger system reset and instead it shall return from the FSP API to the BL/Wrapper with the required reset type. The changes are to handle the ResetRequired return code from FSP APIs and provide lib interface for platform to trigger the actual reset. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Amy Chan <amy.chan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-06-16IntelFsp2WrapperPkg: Add Dymanic PCD capability to PcdFspsBaseAddressSatya Yarlagadda1-1/+4
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed by: Maurice Ma <maurice.ma@intel.com> Reviewed by: Jiewen Yao <jiewen.yao@intel.com> Reviewed by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
generated by cgit v1.1 at 2024-09-17 17:10:41 +0000