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2022-10-05IntelFsp2WrapperPkg: Add header for PlatformMultiPhaseLib.Chasel Chiu1-1/+1
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4092 To comply with coding style rule each library class should have its own header even if it is just a private child library instance consumed by parent public library in the same package. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-09-01IntelFsp2WrapperPkg: Remove duplicated wordsPierre Gondois1-1/+1
In an effort to clean the documentation of the above package, remove duplicated words. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-08-31IntelFsp2WrapperPkg: Add FSP 2.4 MultiPhase interface.Chasel Chiu1-1/+9
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916 Provide FSP 2.4 MultiPhase wrapper support library. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2021-12-20IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build TypeS, Ashraf Ali1-0/+8
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642 when the module is not building in IA32 mode which will lead to building error. when a module built-in X64 function pointer will be the size of 64bit width which cannot be fit in 32bit address which will lead to error. to overcome this issue introducing the 2 new PCD's for the 64bit modules can consume it. based on the which pcd platform set, use that. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Kuo Ted <ted.kuo@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Digant H Solanki <digant.h.solanki@intel.com> Cc: Sangeetha V <sangeetha.v@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2021-09-22IntelFsp2WrapperPkg: Make PcdFspModeSelection dynamicZhang Xiaoqiang1-6/+6
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3632 PcdFspModeSelection will be used to set FSP mode. Make PcdFspModeSelection dynamic and set it accordingly. Signed-off-by: Zhang Xiaoqiang <xiaoqiang.zhang@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2021-05-31IntelFsp2WrapperPkg: Remove microcode related PCDsLou, Yun1-7/+1
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334 IntelFsp2WrapperPkg defines following PCDs: PcdCpuMicrocodePatchAddress PcdCpuMicrocodePatchRegionSize PcdFlashMicrocodeOffset But the PCD name caused confusion because UefiCpuPkg defines: PcdCpuMicrocodePatchAddress PcdCpuMicrocodePatchRegionSize PcdCpuMicrocodePatchAddress in IntelFsp2WrapperPkg means the base address of the FV that holds the microcode. PcdCpuMicrocodePatchAddress in UefiCpuPkg means the address of the microcode. The relationship between the PCDs is: IntelFsp2WrapperPkg.PcdCpuMicrocodePatchAddress + IntelFsp2WrapperPkg.PcdFlashMicrocodeOffset == UefiCpuPkg.PcdCpuMicrocodePatchAddress IntelFsp2WrapperPkg.PcdCpuMicrocodePatchRegionSize - IntelFsp2WrapperPkg.PcdFlashMicrocodeOffset == UefiCpuPkg.PcdCpuMicrocodePatchRegionSize To avoid confusion and actually the PCDs in IntelFsp2WrapperPkg are only used by a sample FSP-T wrapper, this patch removes the 3 PCDs defined in IntelFsp2WrapperPkg. The FSP-T wrapper is updated to directly use the ones in UefiCpuPkg. Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2020-09-01IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec: add FspMeasurementLib.hQi Zhang1-0/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2944 Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Eric Dong <eric.dong@intel.com> Signed-off-by: Qi Zhang <qi1.zhang@intel.com> Message-Id: <20200831020721.8967-1-qi1.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2020-08-26IntelFsp2Wrapper/dsc: Add FspTpmMeasurementLib and PcdFspMeasurementConfig.Jiewen Yao1-1/+18
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2376 Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Qi Zhang <qi1.zhang@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200818062618.3698-7-qi1.zhang@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> [lersek@redhat.com: extend (C) notice in DEC to 2020 per Chasel's request] Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2019-04-09IntelFsp2WrapperPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney1-7/+1
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-11-26IntelFsp2WrapperPkg: Fix line ending format issueChasel, Chiu1-11/+11
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1352 Fixed line ending format wrong issues on some files. Test: Verified building successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Cc: Wu Hao A <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
2018-11-20IntelFsp2WrapperPkg: Support FSP Dispatch modeChasel, Chiu1-2/+11
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1300 Provides PCD selection for FSP Wrapper to support Dispatch mode. Also PcdFspmBaseAddress should support Dynamic for recovery scenario (multiple FSP-M binary in flash) Test: Verified on internal platform and both API and DISPATCH modes booted successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-11-20IntelFsp2WrapperPkg: Revert 90c5bc08Chasel, Chiu1-11/+2
Commit message issue and reverted commit 90c5bc081d15d077606131a61114ddfdefe62e61. Will re-submit with correct formats. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-11-20IntelFsp2WrapperPkg: Support FSP Dispatch modeChasel, Chiu1-2/+11
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1300 Provides PCD selection for FSP Wrapper to support Dispatch mode. Also PcdFspmBaseAddress should support Dynamic for recovery scenario (multiple FSP-M binary in flash) Test: Verified on internal platform and both API and DISPATCH modes booted successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
2018-06-28IntelFsp2WrapperPkg: Clean up source filesLiming Gao1-2/+2
1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
2017-11-29IntelFsp2WrapperPkg: Support UPD allocation outside FspWrapperChasel, Chiu1-2/+11
UPD allocation and patching can be done outside FspWrapper as implementation choice so adding a PCD to select between original FspWrapper allocation model or outside model Cc: Jiewen Yao <Jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-10-28IntelFsp2WrapperPkg: Add a PCD to control if signaling PciEnumerationComplete.Dong, Guo1-0/+18
PciEnumerationComplete might be signaled to FSP in Coreboot. So FSP wrapper driver don't need send it again. Add a PCD to control if a FSP API could be skipped from FspWrapperNotifyDxe driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-06-16IntelFsp2WrapperPkg: Add Dymanic PCD capability to PcdFspsBaseAddressSatya Yarlagadda1-1/+4
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed by: Maurice Ma <maurice.ma@intel.com> Reviewed by: Jiewen Yao <jiewen.yao@intel.com> Reviewed by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-05-23IntelFsp2WrapperPkg: Update gFspWrapperTokenSpaceGuid to ↵Jiewen Yao1-11/+11
gIntelFsp2WrapperTokenSpaceGuid. We updated gIntelFspPkgTokenSpaceGuid to gIntelFsp2PkgTokenSpaceGuid in IntelFsp2Pkg, but we miss the update in IntelFsp2WrapperPkg. This patch fixed the issue and made them consistent. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Satya P Yarlagadda <satya.p.yarlagadda@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-05-13Add IntelFsp2Pkg and IntelFsp2WrapperPkg.Jiewen Yao1-0/+77
Add FSP2.0 support. This series of patch is to support FSP2.0 specification at https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf Some major updates include: 1) One FSP binary is separated to multiple components: FSP-T, FSP-M, FSP-S, and optional FSP-O. Each component has its own configuration data region. 2) All FSP-APIs use same UPD format - FSP_UPD_HEADER. 3) Add EnumInitPhaseEndOfFirmware notifyphase. 4) FSP1.1/FSP1.0 compatibility is NOT maintained. 5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg, to indicate that it is for FspWrapper only. IntelFspPkg and IntelFspWrapperPkg will be deprecated. The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg and IntelFsp2WrapperPkg. The old platform can still use IntelFspPkg and IntelFspWrapperPkg for compatibility consideration. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
generated by cgit v1.1 at 2024-11-13 23:09:07 +0000