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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3153
In FSP the temporary memory provided by bootloader typically will be
totally given to PeiCore as Heap, but in some cases FSP may have to
reserve some more temporary memory for private usage.
This commit adds this flexibility for FSP to reserve some
temporary memory before giving them to PeiCore.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3107
Current script only compares main DSC and output file datetime
to determine if re-generation required or not.
When UPD defined in sub DSC and was modified current script cannot
detect and will not re-generate output files which caused incremental
build issue.
Since UPD can be defined in any sub DSC the script has been updated
to compare all DSC datetime with output files to determine re-generation
is needed or not.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Tested-by: Yuwei Chen <yuwei.chen@intel.com>
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The commit 76e8aac158b0717fa27f12e4d008f79161ddb050 changed Fv map format.
It added the image type to better support source level debug. But it broke
the function of PatchFv.py because PatchFv.py also consume Fv map file.
This patch is to update PatchFv.py to make it work again.
Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Yunhua Feng <fengyunhua@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
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Current FSP rebasing script SplitFspBin.py has support for both
PE32 and PE32+ image formats. However, while updating the ImageBase
field in the image header, it always assumed the ImageBase field is
32bit long. Since PE32+ image format defined ImageBase as 64bit,
the current script will only update the lower 32bit value and leave
the upper 32bit untouched. It does not work well for PE32+ image
that requires update in the upper 32bit ImageBase field. The
expected behavior is to update the full 64bit field. This patch
implemented this fix.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3017
Platform microcode FV may have padding between each version of microcode
binary, and current FSP-T/LoadMicrocodeDefault() cannot handle this case
and return not_found unexpectedly.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Cosmo Lai <cosmo.lai@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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Error message:
raise Exception ("'%s' is not a valid directory!" % FvDir)
NameError: name 'FvDir' is not defined
FvDir should be fvDir.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Yunhua Feng <fengyunhua@byosoft.com.cn>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2967
When no change in FSP UPD DSC files, GenCfgOpt.py should skip
recreating UPD header and BSF files.
This patch added a check to handle this case.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
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IncLines as empty list for the case when InputHeaderFile is not specified.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2827
Fix a bug about parse the macro value which use another macro.
Use the following example to verify:
[Define]
DEFINE M1 = V1
DEFINE M2 = $(M1)/V2
!include $(M2)/pcd.dsc
The old code will failed parse M2 and cause following error:
Traceback (most recent call last):
File "Edk2\IntelFsp2Pkg\Tools\GenCfgOpt.py", line 1550, in <module>
sys.exit(Main())
File "Edk2\IntelFsp2Pkg\Tools\GenCfgOpt.py", line 1513, in Main
if GenCfgOpt.ParseDscFile(DscFile, FvDir) != 0:
File "Edk2\IntelFsp2Pkg\Tools\GenCfgOpt.py", line 533, in ParseDscFile
NewDscLines = IncludeDsc.readlines()
ValueError: I/O operation on closed file.
The tool should support the value use another macro, and expand it.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Ming Tan <ming.tan@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2825
UefiCpuLib has API InitializeFloatingPointUnits.
Remove internal copy of InitializeFloatingPointUnits
in FspSecCoreM, use UefiCpuLib API.
This change also avoid later potential conflict when
use UefiCpuLib for FspSecCoreM module.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781
Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events
and multi-phase silicon initialization.
For backward compatibility the original structures are kept and
new ARCH_UPD structures will be included only when UPD header
revision equal or greater than 2.
GenCfgOpt script also updated to prevent from generating duplicate
FSPT_ARCH_UPD and FSPS_ARCH_UPD typedef structures.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2788
DSC is incomplete according to the established CI policies.
Fsp22SecCoreS.inf needs to be added to the Components section
for completeness.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2726
When FSP switching stack and calling bootloader functions,
the function parameter in stack may not be accessible easily.
We can store the function parameter pointer to FspGlobalData
and retrieve it after stack switched.
Also need to add Loader2PeiSwitchStack () to header file
as public function for platform FSP code to consume.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698
To enhance FSP silicon initialization flexibility an optional
Multi-Phase API is introduced and FSP header needs update for
new API offset. Also new SecCore module created for
FspMultiPhaseSiInit API
New ARCH_UPD introduced for enhancing FSP debug message
flexibility now bootloader can pass its own debug handler
function pointer and FSP will call the function to handle
debug message.
To support calling bootloader functions, a FspGlobalData field
added to indicate if FSP needs to switch stack when FSP running
on separate stack from bootloader.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1706
Issues were:
1. copy_paste_error: PeOptHdr vs PePlusOptHdr.
2. invalid_operation: Invalid operation on
null-like value "roffset".
3. invalid_operation: Invalid operation on
null-like value "rsize".
Fixed them by initializing roffset and rsize as PE32
image type and overriding them when PE32+ header found.
Test:
Compared script output before and after this patch and
the result is identical.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1706
Issue was: invalid_operation: Invalid operation on
null-like value "Base".
Fixed it by initializing Base to 0 before entering
while loop.
Test:
Compared script output before and after this patch and
the result is identical.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2310
When target FV 99% used and only few bytes space left,
SplitFspBin.py may crash with below error:
File "SplitFspBin.py", line 457, in ParseFv
ffshdr = EFI_FFS_FILE_HEADER.from_buffer (self.FvData, offset)
ValueError: Buffer size too small
(40960 instead of at least 40968 bytes)
It was because the offset used by FFS_HEADER parser out of bounds.
It should stop parsing when offset equal or larger than
(buffer size - FFS_HEADER size).
This patch also fixed another crash issue when running script with
Python 3.x and no input parameter given:
File "SplitFspBin.py", line 868, in main
if args.which in ['rebase', 'split', 'genhdr', 'info']:
AttributeError: 'Namespace' object has no attribute 'which'
Test:
1. Ran script with both py2 and py3 with no input and no crash observed.
2. Compare the script result before and after the patch are identical.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
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SecFsp.h is used but missing inf file, which will cause generating
warning message.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=2041
When running with Python 3.x and relying on GenCfgOpt.py to
automatically assign UPD offsets, the script crashed
because some float type variable not compatible with
the operations.
Converted those float variable to int to fix these issues.
Cc: Amy Chan <amy.chan@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Ching JenX Cheng <ching.jenx.cheng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2018
Current FSP SEC_IDT_TABLE structure is not natural aligned:
typedef struct _SEC_IDT_TABLE {
EFI_PEI_SERVICES *PeiService;
UINT64 IdtTable[];
} SEC_IDT_TABLE;
Compiler will insert DWORD padding between 2 elements and
GetPeiServicesTablePointer() in early phase then always
returns padding data from stack, which was not reset to 0
in SecMain.
Solution is to align FSP SEC_IDT_TABLE structure to UefiCpuPkg
to have UINT64 as PeiService field and reset it to 0.
Test: Verified on internal platform and booting successfully
with FSP API mode.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
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Fix various typos in IntelFsp2Pkg.
Signed-off-by: Cœur <coeur@gmx.fr>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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This reverts commit f527942e6bdd9f198db90f2de99a0482e9be5b1b.
Commit message was incorrect.
Signed-off-by: Cœur <coeur@gmx.fr>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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Fix one typo in FmpDevicePkg.
Signed-off-by: Cœur <coeur@gmx.fr>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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https://bugzilla.tianocore.org/show_bug.cgi?id=1930
Updated FSP Python scripts to support both 2.x and
3.x.
Test:
. Verified with Python 2.7.12 and 3.6.6.
. Verified tool result is the same before the change.
. Both py -2 and py -3 built binary can boot.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1883
Add header file for FSP_TEMP_RAM_EXIT_PPI which is
defined by FSP 2.1 spec.
Test: Build successfully.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1308
Support rebasing FSP 1.x binary.
FSP 1.x has single component in binary so not supported
by split command and rebase can be done with the same
command for rebasing FSP-T component in FSP 2.x image.
Test: both FSP 2.x (Kabylake) and FSP 1.x (BroadwellDE) binary
can be rebased successfully.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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This reverts commit:
591b8cb7f3d026d2fa4483c59f3d5fb14be181bf.
Will submit again after freeze done.
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1308
Support rebasing FSP 1.x binary.
FSP 1.x has single component in binary so not supported
by split command and rebase can be done with the same
command for rebasing FSP-T component in FSP 2.x image.
Test: both FSP 2.x (Kabylake) and FSP 1.x (BroadwellDE) binary
can be rebased successfully.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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https://bugzilla.tianocore.org/show_bug.cgi?id=1373
Replace BSD 2-Clause License with BSD+Patent License. This change is
based on the following emails:
https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html
https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html
RFCs with detailed process for the license change:
V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html
V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html
V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395
Add new APIs' implementation (DebugVPrint, DebugBPrint)
in the DebugLib instance. These APIs would expose print
routines with VaList parameter and BaseList parameter.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Michael Turner <Michael.Turner@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1485
Current FSP utilizes pre-allocated temporary memory from
boot loader for both heap and stack. To reduce overall
temporary memory usage FSP may share the same stack with
boot loader and only needs a smaller memory for heap,
no separate memory required for stack.
Setting PcdFspHeapSizePercentage to 0 to enable FSP sharing
stack with boot loader, in this case boot loader stack
has to be large enough for FSP to use. Default is 50
(half memory heap and half memory stack) for backward
compatible with original model.
Test: Verified on internal platform and booting successfully
with both modes.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1391
FSP on-going enhancement for stack utilization required
to know bootloader stack pointer and this pointer can be
retrieved by first input parameter address when FSP-M
entry API invoked by bootloader.
Test: Verified on internal platform and booting successfully
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1477
There was unused keyword added in FspmArchConfigPpi.h
header block and should be removed.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381
In Dispatch mode FSP may consume PPI directly so creating
FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD.
Also Keeps new structure size 8 bytes alignment as other
structures.
Test: Verified on internal platform to boot with this PPI
installed successfully.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1280
When copying IDT table in SecMain, the pointer might be
NULL so added the check to fix it.
Test: Verified on internal platform and boots successfully.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1276
Fixed potentially uninitialized variable build failure
caused by commit: b1cc6f672f3b924cdb190e5b92db3b47f46a8911
Test: Verified on internal platform and boots successfully.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1265
FSP should not override IDT table when it is initialized
by boot loader. IDT should be re-initialized in FSP only
when it is invalid.
To mitigate temporary memory usage a PCD
PcdFspMaxInterruptSupported created for platform to decide
how many interrupts the FSP IDT table can support.
Test: Verified on internal platform and boots successfully.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1241
Add support for both API (original mode) and DISPATCH mode:
1. Add FspMode field from reserved byte of Global
Data Structure to tell which mode is selected by boot
loader. If boot loader invoking FSP-M API this field
will remain as default 0 (API mode), otherwise platform
FSP should set this field to 1 (Dispatch mode) when
initializing Global Data Structure.
2. gFspInApiModePpiGuid will be instaled when FSP running in API
mode and modules only for API mode should have this in depex.
3. If it is DISPATCH mode, FSP will return to PEI dispatcher,
not directly return to boot loader.
4. DISPATCH mode supports DXE NotifyPhase drivers so FSP
will not wait for PEI NotifyPhase callbacks, instead it
will install gFspReadyForNotifyPhasePpiGuid PPI for
platform to complete late initialization before transferring
to DXE.
Test: Verified FSP API and DISPATCH modes on 2 internal
platforms and both boot successfully.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1231
Build system already support override PCD value by command
line so add this support to GenCfgOpt.py
Also update revision to 0.53
Test: Verified UPD header files generated can reflect different
PCD values from --pcd build command input
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Zhu Yonghong <yonghong.zhu@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212
UPD header files generated by GenCfgOpt.py may have
tailing white space from some of the UPD description in DSC,
especially when python script automatically switching lines
for long description string. This patch will always remove
tailing white space for UPD header files.
Test: Verified the patch can remove tailing space in
output header files when UPD DSC contains intentional
tailing white space.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211
For reducing maintenance effort, the UPD offset can be
automatic assigned by GenCfgOpt.py following by alignment
requirements.
The usage model as below:
. If UPD offset in DSC file are all '*', GenCfgOpt.py will
assign offset for all UPD automatically. In this case no
need to manually hardcode offset to all UPD in DSC.
. If UPD offset in DSC file are all not '*', GenCfgOpt.py
will use hardcoded offset directly (original usage model)
. Tool does not support mixing scenario so UPD offset in DSC
should be all '*' or all hardcoded but not mixed.
In auto mode UPD offset will be assigned following natural
alignment (size aligned) rule and the whole structure size
will align to either 32bits or 64bits depends on maximal UPD
size in the structure.
Test: Verified by both UPD offset hardcoded or '*' in DSC and
generated UPD header files are correct.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210
FixedAtBuild PCD is suggested to be used instead
of FeatureFlag PCD so extend this tool to support.
Also skipped PCDs which commented out by '#'.
Test: Verified with FixedAtBuild PCD for including or
excluding lines in generated UPD header files successfully.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
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The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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The PCDs below are unused, so they have been removed from inf.
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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Commit formats had issues so reverted 9 commits
from IntelFsp2Pkg and IntelFsp2WrapperPkg.
Will re-submit them with correct formats.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212
UPD header files generated by GenCfgOpt.py may have
tailing white space from some of the UPD description in DSC,
especially when python script automatically switching lines
for long description string. This patch will always remove
tailing white space for UPD header files.
Test: Verified the patch can remove tailing space in
output header files when UPD DSC contains intentional
tailing white space.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211
For reducing maintenance effort, the UPD offset can be
automatic assigned by GenCfgOpt.py following by alignment
requirements.
The usage model as below:
. If UPD offset in DSC file are all '*', GenCfgOpt.py will
assign offset for all UPD automatically. In this case no
need to manually hardcode offset to all UPD in DSC.
. If UPD offset in DSC file are all not '*', GenCfgOpt.py
will use hardcoded offset directly (original usage model)
. Tool does not support mixing scenario so UPD offset in DSC
should be all '*' or all hardcoded but not mixed.
In auto mode UPD offset will be assigned following natural
alignment (size aligned) rule and the whole structure size
will align to either 32bits or 64bits depends on maximal UPD
size in the structure.
Test: Verified by both UPD offset hardcoded or '*' in DSC and
generated UPD header files are correct.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
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