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2014-11-13ArmPkg/ArmGicLib: select GICv2 mode if SRE is present but unavailableArd Biesheuvel3-10/+26
Even if the CPU id registers indicate hardware support for the System Register interface to the GIC, higher exception levels may disable that interface and only allow access through MMIO. So move the enabling of the SRE bit to the GIC version detection routine: if we trigger an exception, we would have anyway at a later stage, so the net effect is the same. However, if setting the bit doesn't stick, it means we can switch to MMIO and proceed normally otherwise. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16344 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-13ArmPkg/ArmGic: Removed 'GCC' toolchain to build assembly filesOlivier Martin2-2/+2
ARMCC6 toolchain (LLVM based) understands the GNU assembly language. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16343 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11ArmPkg/ArmArchTimerLib: Promotes 32bit value to prevent overflowOlivier Martin1-1/+1
Both MicroSeconds and PcdArmArchTimerFreqInHz are 32-bit values on AArch32 so their multiplication produces 32-bit result that might cause wrong calculation. Example: With MicroSeconds = 200 us, PcdArmArchTimerFreqInHz = 24MHz. 200*24000000 = 0x1_1E1A_3000 => So 0x1E1A_3000 when the type is UINT32. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16329 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11ArmPkg/CompilerIntrinsicesLib: Fixed memmove() and memset()Olivier Martin5-49/+88
- Fixed memmove when going backward: the copy started one byte after the end of the region to copy - memset: - removed unused register - fixed arguments size and character arguments were actually reversed - Added memmove() to ARM32 GCC Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16328 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11ArmPkg: Ensured the stack is always quad-word alignedOlivier Martin3-12/+12
From the AArch64 Procedure Call Standard (ARM IHI 0055B): 5.2.2.1 Universal stack constraints At all times the following basic constraints must hold: - SP mod 16 = 0. The stack must be quad-word aligned. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16327 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11ArmPlatformPkg: Increase more ARM address Pcd entries to 64-bit.Leif Lindholm2-7/+7
Some AArch64 platforms have RAM and flash devices >4GB. Update some additional Pcd entries to 64-bit, and change the corresponding PcdGet32 calls to PcdGet64. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16325 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-31EDK II Contributions.txt: Update patch format informationJordan Justen1-13/+29
Update to show what the patch looks like in email form. NOTE: This does not modify the wording of the "TianoCore Contribution Agreement 1.0" section Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16297 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/ArmLib: Removed duplicated invalidate TLB functionOlivier Martin5-36/+3
ArmInvalidateInstructionAndDataTlb() was doing the same thing as ArmInvalidateTlb(). Both invalidate Data and Instruction TLBs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16253 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/SemihostFs: Implement SetInfo() and handle seeking past the end of a fileRonald Cron2-118/+795
Implement the resizing of the file with SetInfo(). Implement the renaming of a file with SetInfo(). Allow to seek past the end of a file. The support of file resizing implies a rework of the read, write and close functions. So does the support of seeking past the end of a file. That why those two changes are done in the same patch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16244 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/SemihostFs: Fix open file issues revealed by SCTRonald Cron2-54/+131
Fix return codes in case of errors. Fix translation from EFI open mode to semi-hosting open mode to avoid the truncate to zero length of an already existing file opened in read/write or read/write/create mode. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16241 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/SemihostLib: Add library functionsRonald Cron3-0/+148
Add library functions to rename a file and get a temporary name for a file through the semi-hosting interface. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16238 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/Semihostlib: Rename semi-hosting open optionRonald Cron3-3/+3
Change mnemonic SEMIHOST_FILE_MODE_CREATE with mnemonic SEMIHOST_FILE_MODE_UPDATE. The bit referred to by this mnemonic is for the semi-hosting open mode code the equivalent of the + in the ISO C fopen mode terminology. This allows to select the so called update mode for which both read and write are allowed on the open file. The mnemonic SEMIHOST_FILE_MODE_UPDATE is more in line with the ISO C fopen mode terminology. A description of the ISO C fopen modes can be found here : http://pubs.opengroup.org/onlinepubs/009695399/functions/fopen.html. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16237 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/ArmGic: Added GicV3 support to ArmGicDxeOlivier Martin11-63/+353
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16234 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/ArmGic: Added GicV3 support to ArmGicLibOlivier Martin7-0/+375
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16233 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/ArmGic: Added GicV3 detectionOlivier Martin6-12/+85
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16232 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/ArmGic: Introduced ArmGicGetSupportedArchRevision()Olivier Martin4-14/+69
This function returns the revision of the GIC Architecture. Some GICv3 controllers can work in GICv2 mode. Switching to an older GIC revision is driven by the higher level exception level. This function allows code to support any GIC revision at runtime. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16231 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-10ArmPkg/ArmLib/AArch64: Initialize the new N+1-level page table before ↵Olivier Martin1-6/+8
registering it Prior to this change, when a new page table was created at level N+1, the reference to the table was added to the level N translation table, before being initialized. It means if virtual addresses were in the address range defined by this new table the CPU would crash as the address range was not initialized. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16206 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-10ArmPkg/UncachedMemoryAllocationLib: Track uncached memory allocationsOlivier Martin3-106/+211
Keeping track of uncached memory allocations prevents doing expensive cache operations (eg: clean & invalidate) on newly allocated regions by reusing regions where possible Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16205 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-10ArmPkg/ArmPsciResetSystemLib: Made the library only using SMCOlivier Martin3-44/+7
Only ArmVirtualizationPkg based platforms are expected to use the dynamic method to choose between SMC and HVC to invoke PSCI. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16204 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-18ArmPkg/TimerDxe: add workaround for KVM timer interrupt handlingArd Biesheuvel1-0/+1
KVM on ARM currently masks the timer interrupt on the timer side when delivering an interrupt to the guest. This itself is a workaround for an issue where the interrupt is reraised and trapped by the host as soon as the guest is entered, resulting in the guest being starved. Work around this by calling ArmGenericTimerEnable () after servicing each interrupt. The virtual version of ArmGenericTimerCounterLib will then make sure to unmask the interrupt again. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16144 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-16ArmPsciResetSystemLib: read PSCI method in constructorArd Biesheuvel2-1/+14
As this library is used in the implementation of a Runtime Service, make sure to access dynamic PCDs only in the constructor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16108 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10ArmPkg/TimerDxe: Read timer frequency from CPUArd Biesheuvel2-2/+1
The PCD gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz is used in the SEC phase (if applicable) to write the platform's counter frequency to the CNTFRQ system register, as this needs to be done by the highest exception level implemented. Under virtualization, we should be able to rely on the host to have initialized this register to a sane value, as we run at EL1 and only use the virtual timer, so the PcdArmArchTimerFreqInHz PCD has little meaning here. So in either case, by the time we enter the DXE phase, we can use the CNTFRQ system register to read the frequency instead of looking at the PCD. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16090 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10ArmPkg: Introduced ArmPsciResetSystemLibArd Biesheuvel4-0/+158
This implementation of EfiResetSystemLib uses ARM PSCI calls to perform reboot and poweroff, using either HVC or SMC calls. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16089 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10ArmPkg: Add ArmHvcLibArd Biesheuvel6-1/+229
This is a utility library closely modeled after ArmSmcLib, that allows hypervisor call (HVC) instructions to be issued from C code. Change-Id: I5f5c65f83e910ff98dbb2f5b031dad8c4f663daa Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16088 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10ArmPkg: Add PSCI 0.2 constants for system poweroff and resetArd Biesheuvel1-0/+2
Change-Id: I683a603300812578c15cf3c1e0ccb7574fdb5caf Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16087 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10ArmPkg/ArmSmcLib: fix stack handling in .asm version of SMC wrapperArd Biesheuvel1-1/+1
This fixes a bug in the stack handling in the RVCT .asm version of the SMC wrapper. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16086 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09ArmPkg,ArmPlatformPkg: Allow dynamic PCDs for memory base and sizeArd Biesheuvel2-7/+8
This changes the definition and a bunch of references to gArmTokenSpaceGuid.PcdSystemMemoryBase and gArmTokenSpaceGuid.PcdSystemMemorySize so they can be declared as dynamic PCDs by the platform. Also, move the non-SEC call to ArmPlatformInitializeSystemMemory() earlier, so a platform has a chance to set these PCDs before they are first referenced. The purpose is allowing dynamically instantiated virtual machines to declare the system memory by passing a device tree. Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16079 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09ArmPkg: Move TimerDxe and ArmArchTimerLib to new ArmGenericTimerCounterLibArd Biesheuvel14-307/+34
Move TimerDxe and ArmArchTimerLib to ArmGenericTimerCounterLib, and update all platforms to select the physical counter instance they have been using implicitly all along. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16078 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09ArmPkg/TimerDxe: Register the virt and hyp timer interrupts at init time.Ard Biesheuvel2-0/+8
Change-Id: I1162dc60140278c0b3da837bf325e3789ababf54 Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16077 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09ArmPkg: add ArmGenericTimerCounterLib implementation using virtual timerArd Biesheuvel3-0/+183
This adds an implementation of ArmGenericTimerCounterLib using the virtual architected generic timer. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16076 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09ArmPkg: add ArmGenericTimerCounterLib implementation using physical timerArd Biesheuvel3-0/+174
This adds an implementation of ArmGenericTimerCounterLib using the physical architected generic timer. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16075 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09ArmPkg: add ArmGenericTimerCounterLib interfaceArd Biesheuvel1-0/+85
This introduces ArmGenericTimerCounterLib by adding the include file ArmPkg/Include/Library/ArmGenericTimerCounterLib.h. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16074 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09ArmPkg: Renamed ArmArchTimerLib.h to ArmArchTimer.hArd Biesheuvel8-10/+10
The ArmArchTimerLib.h include file is not directly related to the TimerLib instance ArmArchTimerLib, so the name is confusing. Rename to ArmArchTimer.h instead. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16073 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09ArmPkg: allow dynamic GIC base addressesArd Biesheuvel4-25/+36
Allow the PCDs gArmTokenSpaceGuid.PcdGicDistributorBase and gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase to be redeclared as PcdsDynamic by the platform, so virtual machines can set these properties during boot. As the PcdGet32() calls now call into the PCD database, cache the values that are required during the handling of interrupts. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16072 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09ArmPkg: allow dynamically discovered timer interruptsArd Biesheuvel1-10/+13
To support booting on virtual machines whose interrupt routing is discovered from the device tree, allow the interrupt numbers to be redeclared as PcdsDynamic by the platform .dsc Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16071 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09ArmPkg/ArmDisassemblerLib: ARMThumb and AArch64 fixesHarry Liebel3-7/+56
- Fix ARM Thumb mask operator. This was flagged by a toolchain as warning "use of logical '&&' with constant operand [-Wconstant-logical-operand]" - AArch64 should not be building the ARM32 disassemblers. - Add a AArch64 build target. The disassembler is still to be implemented. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16069 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-01ARM Packages: Removed unused PcdArmPrimaryCoreOlivier Martin2-6/+1
This PCD has been replaced by ArmPlatformIsPrimaryCore() function. Althrough this PCD is still used in some occasions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16026 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-01ArmPkg/BdsLib/Arm: Check Linux image and parameters are not overlappingOlivier Martin1-2/+8
Check Linux image and parameters are not overlapping with each other. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16013 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-01ArmPkg/BdsLib/Arm: Clean Data cache before disabling itOlivier Martin1-3/+5
It is actually the same sequence as AArch64. Without cleaning the data cache prior to disable the cache, the LR value pushed on the stack when entering in ArmCleanInvalidateDataCache() might have been overwritten by this specific cache line maintenance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16012 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-27ArmPkg/TimerDxe: Fixed real time periodOlivier Martin1-8/+50
Prior to this change, the TimerPeriod was re-initialize at the end of the interrupt handling with the value of the period. It means the real timer period was: Timer Interrupt Processing time + Timer Period Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15923 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-27ArmPkg/TimerDxe: Fixed the reloading of the periodOlivier Martin1-1/+1
Prior to this change the period was restored to the default period. This change restores the latest 'set period'. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15922 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-27ArmPkg/TimerDxe: Changed calculation to allow 1KHz granularity frequencyOlivier Martin2-7/+10
Prior to this change the frequency was rounded to 1Mhz. This change rounds the timer frequency to 1KHz. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15921 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-26ArmPkg/ArmArchTimerLib: Remove non required [depex] and IoLibOlivier Martin1-10/+1
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15903 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-26ARM Packages: Replace tabs by spaces for indentationRonald Cron5-17/+17
Replace tabs by spaces for indentation to comply to EDK2 coding standards. Done in files with extension ".S", ".c", ".h", ".asm", ".dsc", ".inc", "*.inf", "*.dec" or ".fdf" and located in ArmPkg, ArmPlatformPkg, EmbeddedPkg, BeagleBoardPkg or Omap35xxPkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15901 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-25EDK II Contributions.txt: Note acceptable contribution licensesJordan Justen1-0/+14
We strongly prefer that contribtions be offered using the same license as the project/module. But, we should document other acceptable licenses for contributions. This will allow package owners to more easily know if they can accept a contribution under a different source license. NOTE: This does not modify the wording of the "TianoCore Contribution Agreement 1.0" section Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Mark Doran <mark.doran@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15892 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-20ARM Packages: Added support for GCC stack protectorOlivier Martin olivier.martin1-4/+4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15853 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-20ArmPkg/ArmLib/ArmV7: Fixed ArmIsMpCore()Olivier Martin2-4/+8
The function was not returning the expected value. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15850 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19ArmPkg/ArmLib: Set again TCR after getting the Translation Table attributesOlivier Martin1-0/+3
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15837 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19ArmPkg/BdsLib: Prevent a hang in BdsConnectDevicePath() when a sub-device ↵Olivier Martin3-9/+22
path is not found Some device paths were making BdsConnectDevicePath() hang. To prevent these hangs we check if the handle returned by gBS->LocateDevicePath() is the same after each iteration. An example of a device path that hangs: PciRoot(0x0)/Pci(0x1,0x0)/USB(0x0,0x0)/USB(0x3,0x0)/HD(...) The connect controller function manages to find PciRoot()/Pci(0x1,0x0) but the USB driver does not produce USB(0x0,0x0)/USB(0x3,0x0) and returns EFI_SUCCESS on its initialization. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15835 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19ARM Packages: Removed trailing spacesRonald Cron183-1517/+1514
Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.1 at 2024-11-10 09:26:16 +0000