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2023-06-01ArmPkg: Fix ArmGicAcknowledgeInterrupt () for GICv3Sami Mujawar1-6/+10
The ArmGicAcknowledgeInterrupt () returns the value returned by the Interrupt Acknowledge Register and the InterruptID separately in an out parameter. The function documents the following: 'InterruptId is returned separately from the register value because in the GICv2 the register value contains the CpuId and InterruptId while in the GICv3 the register value is only the InterruptId.' This function skips setting the InterruptId in the out parameter for GICv3. Although the return value from the function is the InterruptId for GICv3, this breaks the function usage model as the caller expects the InterruptId in the out parameter for the function. e.g. The caller may end up using the InterruptID which could potentially be an uninitialised variable value. Therefore, set the InterruptID in the function out parameter for GICv3 as well. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2023-06-01ArmPkg: Adjust variable type and cast for RegShift & RegOffsetSami Mujawar2-15/+15
According to the GIC architecture version 3 and 4 specification, the maximum number of INTID bits supported in the CPU interface is 24. Considering this the RegShift variable is not required to be more than 8 bits. Therefore, make the RegShift variable type to UINT8. Also add necessary typecasts when calculating the RegOffset and RegShift values. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-06-01ArmPkg: Prevent SgiId from setting RES0 bits of GICD_SGIRSami Mujawar1-1/+3
GICD_SGIR is a 32-bit register, of which INTID is bits [3:0] and Bits [14:4] is RES0. Since SgiId parameter in the function ArmGicSendSgiTo () is UINT8, mask unused bits of SgiId before writing to the GICD_SGIR register to prevent accidental setting of the RES0 bits. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2023-06-01ArmPkg: Remove unused function declarationsSami Mujawar1-14/+0
The IrqInterruptHandler () and ExitBootServicesEvent () function declarations were unused. Therefore, remove these declarations. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-06-01ArmPkg: Typecast IntID to UINT32 in ArmGicV2EndOfInterruptSami Mujawar1-2/+4
The EIOR register of the Gic CPU interface is a 32 bit register. However, the HARDWARE_INTERRUPT_SOURCE used to represent the interrupt source (Interrupt ID) is typedefed as UINTN, see EmbeddedPkg\Include\Protocol\HardwareInterrupt.h Therfore, typecast the interrupt ID (Source) value to UINT32 before setting the EOIR register. Also, add an assert to check that the value does not exceed 32 bits. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-06-01ArmPkg: Make variables used for GicInterrupt UINTNSami Mujawar2-6/+6
Although the maximum interrupt ID on GicV2 is 10bit and for GicV3/4 is 24bit, and that the IAR and EOIR registers of the Gic CPU interface are 32 bit; the typedef HARDWARE_INTERRUPT_SOURCE is defined as UINTN in EmbeddedPkg\Include\Protocol\HardwareInterrupt.h Therefore, use UINTN for Gic Interrupt variables and use appropriate typecasts wherever needed. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-06-01ArmPkg: Fix return type for ArmGicGetInterfaceIdentificationSami Mujawar1-1/+1
The CPU Interface Identification Register (GICC_IIDR) is a 32-bit register. Since ArmGicGetInterfaceIdentification () returns the value read from the GICC_IIDR register, update the return type for this function to UINT32. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-06-01ArmPkg: Fix Non-Boolean comparison in ArmGicEnableDistributorSami Mujawar1-1/+3
According to edk2 coding standard specification, Non-Boolean comparisons must use a compare operator (==, !=, >, < >=, <=). See Section 5.7.2.1 at https://edk2-docs.gitbook.io/ edk-ii-c-coding-standards-specification/5_source_files/ 57_c_programming Therefore, fix the comparison in ArmGicEnableDistributor() Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-06-01ArmPkg: Fix ArmGicSendSgiTo() parametersSami Mujawar1-3/+3
The Software Generated Interrupt Register (GICD_SGIR) is a 32 bit register with the following bit assignment: TargetListFilter, bits [25:24] CPUTargetList, bits [23:16] NSATT, bit [15] SGIINTID, bits [3:0] Therefore, modify the TargetListFilter, CPUTargetList, SGI Interrupt ID parameters of the ArmGicSendSgiTo () to use UINT8 instead of INTN. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-06-01ArmPkg: Fix data type used for GicInterruptInterfaceBaseSami Mujawar3-7/+15
The data type used by variables representing the GicInterruptInterfaceBase has been inconsistently used in the ArmGic driver and the library. The PCD defined for the GIC Interrupt interface base address is UINT64. However, the data types for the variables used is UINTN, INTN, and at some places UINT32. Therefore, update the data types to use UINTN and add necessary typecasts when reading values from the PCD. This should then be consistent across AArch32 and AArch64 builds. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2023-06-01ArmPkg: Fix data type used for GicDistributorBaseSami Mujawar5-15/+17
The data type used by variables representing the GicDistributorBase has been inconsistently used in the ArmGic driver and the library. The PCD defined for the GIC Distributor base address is UINT64. However, the data types for the variables used is UINTN, INTN, and at some places UINT32. Therefore, update the data types to use UINTN and add necessary typecasts when reading values from the PCD. This should then be consistent across AArch32 and AArch64 builds. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-06-01ArmPkg: Fix GicV2 BaseAddress typesNeil Jones1-2/+2
The GIC v2 base addresses can be 64bit, don't limit to 32 on 64bit machines. Signed-off-by: Neil Jones <neil.jones@blaize.com> Reviewed-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2023-04-10ArmPkg: Update code to be more C11 compliant by using __func__Rebecca Cran1-2/+2
__FUNCTION__ is a pre-standard extension that gcc and Visual C++ among others support, while __func__ was standardized in C99. Since it's more standard, replace __FUNCTION__ with __func__ throughout ArmPkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2022-07-01ArmPkg/Drivers: ArmGicIsInterruptEnabled returns incorrect valueRobbie King1-4/+3
The issue appears to have been introduced by: 41fb5d46 : ArmPkg/ArmGic: Use the GIC Redistributor instead of GIC Distributor for GICv3 The changes to ArmGicIsInterruptEnabled() introduced the error where the Boolean result is assigned to Interrupts, but then the bit position check is performed again (against the computed Boolean result instead of the interrupt mask) during the return statement. Fix removes erroneous test and relies on boolean test made at return. Signed-off-by: Robbie King <robbiek@xsightlabs.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2022-05-13ArmPkg: Remove RVCT supportRebecca Cran2-83/+0
RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran <quic_rcran@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-12-07ArmPkg: Apply uncrustify changesMichael Kubacki9-248/+267
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ArmPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
2021-08-27ArmPkg/GicV3Dxe: Don't signal EOI on arbitrary interruptsArd Biesheuvel1-4/+0
Currently, at ExitBootServices() time, the GICv3 driver signals End-Of-Interrupt (EOI) on all interrupt lines that are supported by the interrupt controller. This appears to have been carried over from the GICv2 version, but has been turned into something that violates the GIC spec, and may trigger SError exceptions on some implementations. Marc puts it as follows: The GIC interrupt state machine is pretty strict. An interrupt can only be deactivated (with or without prior priority drop) if it has been acknowledged first. In GIC speak, this means that only the following sequences are valid: With EOImode==0: x = ICC_IAR{0,1}_EL1; ICC_EOIR{0,1}_EL1 = x; With EOImode==1: x = ICC_IAR{0,1}_EL1; ICC_EOIR{0,1}_EL1 = x; ICC_DIR_EL1 = x; Any write to ICC_EOIR{0,1}_EL1 that isn't the direct consequence of the same value being read from ICC_IAR{0,1}_EL1, and with the correct nesting, breaks the state machine and leads to unpredictable results that affects *all* interrupts in the system (most likely, the priority system is dead). See Figure 4-3 ("Interrupt handling state machine") in Arm IHI 0069F for a description of the acceptable transitions. Additionally, on implementations that have ICC_CTLR_EL1.SEIS==1, a SError may be generated to signal the error. See the various <quote> IMPLEMENTATION_DEFINED "SError ...."; </quote> that are all over the pseudocode contained in the same architecture spec. Needless to say, this is pretty final for any SW that would do silly things on such implementations (which do exist). Given that in our implementation, every signalled interrupt is acked, handled and EOId in sequence, there is no reason to EOI all interrupts at ExitBootServices() time in the first place, so let's just drop this code. This fixes an issue reported by Marc where an SError is triggered by this code, bringing down the system. Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-05-27ArmPkg/ArmGic: Fix maximum number of interrupts in GICv3edk2-stable202105Andreas Sandberg1-2/+9
Bugzilla: 3415 (https://bugzilla.tianocore.org/show_bug.cgi?id=3415) The GICv3 architecture supports up to 1020 ordinary interrupt lines. The actual number of interrupts supported is described by the ITLinesNumber field in the GICD_TYPER register. The total number of implemented registers is normally calculated as 32*(ITLinesNumber+1). However, maximum value (0x1f) is a special case since that would indicate that 1024 interrupts are implemented. Add handling for this special case in ArmGicGetMaxNumInterrupts. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Signed-off-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
2021-04-28ArmPkg: Correct small typosPierre Gondois2-2/+2
The 'cspell' CI test detected some small typos in ArmPkg. Correct them. Cc: Bret Barkelew <bret.barkelew@microsoft.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28ArmPkg: Fix Ecc error 8003Pierre Gondois1-3/+3
This patch fixes the following Ecc reported error: The #ifndef at the start of an include file should have one postfix underscore, and no prefix underscore character Some include guards have been modified to match the name of the header file. Some comments have also been added on the closing '#endif'. Cc: Bret Barkelew <bret.barkelew@microsoft.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15ArmPkg: Remove ArmGic/ArmGicSecLib.cPierre Gondois1-58/+0
Commit: 142fa386eb907df55c239311cd5fa2d40f5007dd removes the ArmGicSecLib. The file ArmGic/ArmGicSecLib.c was exclusively used by this library. Thus, this file should also be removed. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-03-01ArmPkg/ArmGicLib: Fix GICR_IPRIORITYR address wrong issueMing Huang1-1/+4
The register address of GICR_IPRIORITYR is in SGI_base frame. Add IPRIORITY_ADDRESS macro for getting GICR_IPRIORITYR address. Otherwise GIC RAS error(Uncorrected software error) may report in ArmGicDxe. This resolves BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3236 Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Tested-by: Ard Biesheuvel <ardb@kernel.org> # QEMU/kvm guest on ThunderX2 Tested-by: Quan Nguyen <quan@os.amperecomputing.com>
2021-03-01ArmPkg/ArmGicLib: Fix two macros issue for offset parameterMing Huang1-2/+2
Modify two macros to put "offset" in parentheses and remove parentheses from "4 * offset". Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2020-12-18ArmPkg/ArmGicV3Dxe: Use ArmGicSetInterruptPriority() to set priorityQuan Nguyen1-8/+5
When Affinity Routing enabled, the GICR_IPRIORITYR<n> is used to set priority for SGIs and PPIs instead of GICD_IPRIORITYR<n>. This patch calls ArmGicSetInterruptPriority() helper function when setting priority to handle the difference. Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Reviewed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
2020-12-18ArmPkg/ArmGicLib: Add ArmGicSetInterruptPriority() helper functionQuan Nguyen1-0/+44
According to ARM IHI 0069F, section 11.9.18 GICD_IPRIORITYR<n>, Interrupt Priority Registers, n = 0 - 254, when affinity routing is enabled for the Security state of an interrupt, GICR_IPRIORITYR<n> is used instead of GICD_IPRIORITYR<n> where n = 0 to 7 (that is, for SGIs and PPIs). As setting interrupt priority for SGIs and PPIs are handled using difference registers depends on the mode, this patch instroduces ArmGicSetInterruptPriority() helper function to handle the discrepancy. Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Reviewed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
2019-07-23ArmPkg: list module-internal header files in INF [Sources]Laszlo Ersek1-0/+1
The BaseTools build feature introduced for TianoCore#1804 / in commit 1fa6699e6cd4 ("BaseTools: Add a checking for Sources section in INF file", 2019-06-10) logs some (non-fatal) warnings about unlisted internal header files. List those files explicitly. Note: header files are added in lexicographical order only if the underlying INF file already keeps the [Sources] and [LibraryClasses] sections in lexicographical order. Otherwise, header files are added in rough "logical" order. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2019-04-09ArmPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney15-105/+15
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2019-02-26ArmPkg: Fix writes to GICv3 GICD_IROUTER<n> regSami Mujawar1-2/+2
According to ARM Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0, GICD_IROUTER<n> is a 64-bit register. Fixed code to use 64 bit MMIO write operations so that the Aff3 value (bits [39:32]) is written to GICD_IROUTER<n>. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reported-by: Carl van Schaik <carl@cog.systems> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-11-15ArmPkg/ArmGicDxe ARM: fix encoding for GICv3 interrupt acknowledgeArd Biesheuvel2-2/+2
Fix a typo in the 32-bit ARM version of the GICv3 driver, which uses the wrong system register encoding to access ICC_IAR1, and attempted to access ICC_IAR0 instead. This results in boot time hangs both under QEMU emulation and on real hardware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2018-11-07ArmPkg/ArmGicDxe: Fix GICv3 interrupt routing mode bugMing Huang1-1/+1
Setting GICD_IROUTERn.IRM and GICD_IROUTERn.{Aff3,Aff2,Aff1,Aff0} at the same time is nonsensical (see 8.9.13 in the GICv3 spec, which says of GICD_IROUTERn.IRM that "When this bit is set to 1, GICD_IROUTER<n>.{Aff3,Aff2,Aff1,Aff0} are UNKNOWN"). There is also no guarantee that IRM is implemented (see GICD_TYPER.No1N which indicates whether the implementation supports this or not). Let's thus not set this bit, as we want all SPIs to be delivered to the same CPU, and not be broadcast to all of them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang <ming.huang@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-12ArmPkg: Add support for GICv4Sami Mujawar2-18/+27
Updated Redistributor base calculation to allow for the fact that GICv4 has 2 additional 64KB frames (for VLPI and a reserved frame). The code now tests the VLPIS bit in the GIC Redistributor Type Register (GICR_TYPER) and calculates the Redistributor granularity accordingly. The code changes are: GICR_TYPER register fields, etc, added to the header. Loop updated to pay attention to GICR_TYPER.Last. Derive frame "stride" size from GICR_TYPER.VLPIS. Note: The assumption is that the redistributors are adjacent for all CPUs. However this may not be the case for NUMA systems. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-04-12ArmPkg/ArmGicDxe: annotate protocol usage in "ArmGicDxe.inf"Laszlo Ersek1-4/+4
"ArmGicDxe.inf" currently does not document how the protocols in the [Protocols] section are used. Such comments help us analyze behavior, so let's add them now. - gHardwareInterruptProtocolGuid and gHardwareInterrupt2ProtocolGuid are always produced on the InterruptDxeInitialize() -> (GicV2DxeInitialize() | GicV3DxeInitialize()) -> InstallAndRegisterInterruptService() call path. - gEfiCpuArchProtocolGuid is consumed in the CpuArchEventProtocolNotify() protocol notify callback. (Technically this is "conditional"; however the firmware cannot work without architectural protocols, so we can call it unconditional.) While at it, drop the gArmGicDxeFileGuid comment from FILE_GUID; we're going to make that GUID uninteresting soon. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Steve Capper <steve.capper@linaro.org> Cc: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2018-02-06ArmPkg/Gic: force GIC driver to run before CPU arch protocol driverArd Biesheuvel3-24/+51
Currently, the GIC driver has a static dependency on the CPU arch protocol driver, so it can register its IRQ handler at init time. This means there is a window between dispatch of the CPU driver and dispatch of the GIC driver where any unexpected GIC state may trigger an interrupt which we are not set up to handle yet. Note that this is even the case if we enter UEFI with interrupts disabled at the CPU, given that any TPL manipulation involving TPL_HIGH_LEVEL will unconditionally enable IRQs at the CPU side regardless of whether they were enabled to begin with (but only as soon as the CPU arch protocol is actually installed) So let's reorder the GIC driver with the CPU driver, and let it run its initialization that puts the GIC into a known state before enabling interrupts. Move its installation of its IRQ handler to a protocol notify callback on the CPU arch protocol so that it runs as soon as it becomes available. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-26ArmPkg: remove unused ArmGicSecLib library implementationArd Biesheuvel2-152/+0
This module is not used anywhere under edk2 or edk2-platforms, so let's remove it. This removes the only dependency on ArmPlatformLib from ArmPkg. While at it, remove a mention of ArmPlatformPkg from a comment in the .dec file as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-10-05ArmPkg/ArmGicDxe: Expose HardwareInterrupt2 protocolArd Biesheuvel5-1/+341
The existing HardwareInterrupt protocol lacked a means to configure the level/edge properties of an interrupt. The new HardwareInterrupt2 protocol introduced this capability. This patch updates the GIC drivers to provide the new interfaces. The changes comprise: Update to use HardwareInterrupt2 protocol Additions to register info in ArmGicLib.h Added new functionality (GetTriggerType and SetTriggerType) The requirement for this change derives from a problem detected on ARM Juno boards, but the change is of generic (ARM) relevance. This commit is in response to review on the mailing list and, as suggested there, rolls Girish's updates onto Ard's original example. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Tested-by: Girish Pathak <girish.pathak@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-10-05ArmPkg: Tidy GIC code before changes.Evan Lloyd5-91/+165
This change is purely cosmetic, to tidy some code before change. Mods involve: Re-order #includes Reformat comments. Use ns consistently (always "100ns" not sometimes "100 nS") Split overlength code lines. Make protocol functions STATIC. Remove "Horor vacui" comments. Rationalize GIC register address calculations Replace explicit test and assert with ASSERT_EFI_ERROR. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-09ArmPkg/ArmGicLib: use correct loop variableArd Biesheuvel1-1/+1
The ArmGicLib API function GicGetCpuRedistributorBase () declares GicCpuRedistributorBase to iterate over the redistributors of all CPUs, but then inadvertently advances GicRedistributorBase instead. Reported-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-upDennis Chen2-4/+4
According to the ACPI 6.0/6.1 spec, the physical base address of GICC, GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC base address PCDs to 64-bit, and fix up all users. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Dennis Chen <dennis.chen@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-08-11ArmPkg/ArmGicV3: switch to ASM_FUNC() asm macroArd Biesheuvel2-40/+16
Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-08ArmPkg/ArmGicDxe: Fix double GIC EIOR write per interruptAlexei Fedorov2-6/+4
This commit fixes a bug in the GIC v2 and v3 drivers where the GICC_EOIR (End Of Interrupt Register) is written twice for a single interrupt. GicV(2|3)IrqInterruptHandler() calls the Interrupt Handler and then GicV(2|3)EndOfInterrupt() on exit: InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt]; if (InterruptHandler != NULL) { // Call the registered interrupt handler. InterruptHandler (GicInterrupt, SystemContext); } else { DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt)); } GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt); although gInterrupt->EndOfInterrupt() can be expected to have already been called by InterruptHandler() [which is the case for the primary in-tree handler in TimerDxe] The fix moves the EndOfInterrupt() call inside the else case for unregistered/spurious interrupts. This removes a potential race condition that might have lost interrupts. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-07-13ArmPkg/ArmGicLib: manage GICv3 SPI state at the distributorArd Biesheuvel1-3/+22
Unlike SGIs and PPIs, which are private to the CPU and are managed at the redistributor level (which is also a per-CPU construct), shared interrupts (SPIs) are shared between all CPUs, and therefore managed at the distributor level (just as on GICv2). Reported-by: Narinder Dhillon <ndhillonv2@gmail.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-06-23ArmPkg/ArmGicV3Dxe: configure all interrupts as non-secure Group-1Ard Biesheuvel1-0/+16
Reassign all interrupts to non-secure Group-1 if the GIC has its DS (Disable Security) bit set. In this case, it is safe to assume that we own the GIC, and that no other firmware has performed any configuration yet, which means it is up to us to reconfigure the interrupts so they can be taken by the non-secure firmware. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-04-25ArmPkg/Gic: Fix boundary checking bugHeyi Guo3-9/+9
mGicNumInterrupts is the total number of interrupts, so the interrupt ID equal to mGicNumInterrupts is also invalid. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2015-12-15ArmPkg/ArmGic: fix bug in GICv3 distributor configurationArd Biesheuvel1-2/+2
In the function ArmGicEnableDistributor (), the Affinity Routing Enable (ARE) bit, which essentially defines whether the GIC runs in v2 or v3 mode, is inadvertently cleared when enabling the GIC distributor if it is running in v3 mode. So fix that. Reported-by: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19274 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-03ArmPkg: update RVCT assembly functions to use new RVCT_ASM_EXPORT macroEugene Cohen1-17/+9
This has the effect of splitting assembly functions into their own sections so the linker can remove unused ones to save space. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@gmail.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19109 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-10ArmPkg/GicV3: use GICv3 generic sysreg names only for GNU asArd Biesheuvel1-0/+10
The GNU assembler extends the generic notation for IMPLEMENTATION DEFINED system registers to support any system register, so that system registers defined by newer versions of the architecture can still be used by older versions of the toolchain. Clang before v3.6 supports the generic notation, but does not support this extension, nor does it need to in the particular case of the GICv3 support code, since it knows the GICv3 registers by their architectural names. So only redefine their real names to their generic aliases if we are not using clang. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18192 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28ArmPkg: split off ArmGicArchLib from ArmGicLibArd Biesheuvel4-106/+2
The current implementation of ArmGicGetSupportedArchRevision () that is used by all ARM platforms is entirely stateless (in order to support being executed from flash) so it needs to interrogate the hardware for the supported GIC revision upon each invocation. However, this statelessness is only needed for SEC type modules; in all other cases, we could easily determine the GIC revision once, and store the result in a global variable. In preparation of having separate early and normal versions, this patch introduces the ArmGicArchLib library class and default implementation, and moves the existing ArmGicGetSupportedArchRevision () into it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18098 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28ArmPkg: merge ArmGicV[23]Lib.h into ArmGicLib.hArd Biesheuvel8-133/+4
Before splitting off ArmGicArchLib and moving it out of ArmPkg/Drivers/ArmGic into ArmPkg/Library, make sure that the GIC specific declarations it depends on are not hidden away in local headers "GicV2/GicV2Lib.h" and "GicV3/GicV3Lib.h". So merge them with <Library/ArmGicLib.h>. This is entirely appropriate, since this is not a header that declares a public interface into ArmGicLib, but defines implementation internals. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18097 6f19259b-4bc3-4df7-8a09-765794883524
2015-06-09ArmPkg: reduce sysreg access count in GIC revision probeArd Biesheuvel2-4/+16
Accesses to system registers are disproportionately heavy-weight when executed under virtualization, since each one involves two world switches (from guest to host and back again). So change the sequence that enables the GIC SRE interface so that it performs only a single sysreg read to test whether the SRE interface is enabled already, and only performs a write and an additional read if that turns out not to be the case. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17596 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-25ArmPkg/ArmGic: Fix GICv3 in GICv2 legacy modeOlivier Martin2-6/+30
- GIC distributor needs to be programmed to target interrupts on the boot CPU using the Interrupt Processor Targets Registers - Enabling the GIC Distributor is different following the value of GICD_CTLR.ARE_NS. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16926 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.1 at 2024-07-16 19:55:01 +0000