Age | Commit message (Collapse) | Author | Files | Lines |
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To make the code platform independent we should not use PcdArmPrimaryCore
in libraries other than the platform specific libraries.
Some platforms allow to change the primary core with external registers.
These platforms do not use PcdArmPrimaryCore to identify the primary CPU.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14938 6f19259b-4bc3-4df7-8a09-765794883524
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- Used correct PCD
- Implement the function for AArch64, BeagleBoard, CTA15A7
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14937 6f19259b-4bc3-4df7-8a09-765794883524
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when SKU ID enabled.
In GetLocalTokenNumber () of Service.c(DXE), the TokenNumber is wrong to call GetPtrTypeSize ().
GetPtrTypeSize need the original TokenNumber.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Bob C Feng <bob.c.feng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14936 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin olivier.martin@arm.com
Reviewed-by: Eric Dong <eric.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14935 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14934 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14933 6f19259b-4bc3-4df7-8a09-765794883524
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SMBIOS table. Update LegacyBiosDxe to move SMBIOS table to reserved memory for backward compatibility.
Signed-off-by: Elvin Li <elvin.li@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14932 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14931 6f19259b-4bc3-4df7-8a09-765794883524
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The SmmLockBox driver in
"MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf" currently
specifies a DepEx on EFI_SMM_SW_DISPATCH2_PROTOCOL.
However, the driver doesn't use this protocol at all, either directly or
indirectly. It calls SmiHandlerRegister()
[MdeModulePkg/Core/PiSmmCore/Smi.c] to register SmmLockBoxHandler()
(which serves LockBox requests).
In turn, the SMM Core function SmiHandlerRegister() is also implemented
without EFI_SMM_SW_DISPATCH2_PROTOCOL.
The DepEx has been present since the initial commit of the SmmLockBox
driver (SVN r12029); it is probably superfluous. Let's remove it.
(Alternatively, we could extend OvmfPkg/EmuSmmDxe to fake this protocol,
and return EFI_UNSUPPORTED when any member is called.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14930 6f19259b-4bc3-4df7-8a09-765794883524
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InitializeDebugAgentPhase2().
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14929 6f19259b-4bc3-4df7-8a09-765794883524
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protocol interface failure case
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14928 6f19259b-4bc3-4df7-8a09-765794883524
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should be behind s/w related stop operation, which could avoid h/w not working if s/w stop operation fails.
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Elvin Li <elvin.li@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14927 6f19259b-4bc3-4df7-8a09-765794883524
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- Added STR_GEN_PARAM_INV_HEX string
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chris Phillips <chrisp@hp.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14926 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14925 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14924 6f19259b-4bc3-4df7-8a09-765794883524
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ALLOW_EXECUTE_ON_SECURITY_VIOLATION is no longer supported.
Signed-off-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Dong, Guo <guo.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14923 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14922 6f19259b-4bc3-4df7-8a09-765794883524
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UINIXGCC IA32 build issue:
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14921 6f19259b-4bc3-4df7-8a09-765794883524
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mDoFarReturnFlag and mErrorCodeFlag to avoid page fault with big RAM sizes (> 2GB).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14920 6f19259b-4bc3-4df7-8a09-765794883524
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version 2 (ACPI 5.0 compatible).
Signed-off-by: Dong Guo <guo.dong@intel.com>
Reviewed-by: Yao, Jiewen <jiewen.yao@intel.com>
Reviewed-by: Fu, Siyuan <siyuan.fu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14919 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Dong, Eric <eric.dong@intel.com>
Reviewed-by: Dong, Guo <guo.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14918 6f19259b-4bc3-4df7-8a09-765794883524
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to return failure.
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14917 6f19259b-4bc3-4df7-8a09-765794883524
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config header string.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14916 6f19259b-4bc3-4df7-8a09-765794883524
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When the Device Tree was loaded above the 32bit address space the operation:
*RelocatedFdt = ALIGN ((UINT64)*RelocatedFdt, (UINT32)FdtAlignment);
was returning an incorrect address.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14915 6f19259b-4bc3-4df7-8a09-765794883524
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PcdPrePiCpuMemorySize & PcdPrePiCpuIoSize
This change introduces default values for the PCDs PcdPrePiCpuMemorySize & PcdPrePiCpuIoSize.
These values are for the architectures ARM, AARCH64, IA32 and X64.
The redefinition of these PCDs (with the same default values) have been removed from the DSC files.
Note: the default value for AARCH64 was 32. It was preventing to allocate buffer above the 32bit
address space.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14914 6f19259b-4bc3-4df7-8a09-765794883524
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EFI modules
When loaded above the 32-bit address space the address requires more than 8 characters.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14913 6f19259b-4bc3-4df7-8a09-765794883524
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space on AArch64
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14912 6f19259b-4bc3-4df7-8a09-765794883524
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The Link Register (LR) does not need adjustement when receiving a Supervisor Call (SVC).
Note: SVC might be generated by debuggers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14911 6f19259b-4bc3-4df7-8a09-765794883524
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bringup when remapping DRAM at 0x0
If the DRAM is remapped at 0x0 then we need to wake up the secondary cores from wfe
(waiting for the memory to be initialized) as the instruction is still in the remapped
flash region at 0x0 to make them jumping into the C-code which lives in the NOR1 at 0x44000000 before
the region 0x0 is remapped as DRAM.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14910 6f19259b-4bc3-4df7-8a09-765794883524
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specific files
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14909 6f19259b-4bc3-4df7-8a09-765794883524
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These functions are not chipset specific.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14908 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14907 6f19259b-4bc3-4df7-8a09-765794883524
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If EDK2_ARMVE_STANDALONE is not defined then the value is set to 1.
The developer has to explicit set the macro to zero to build a non standalone build.
It means this macro is always defined.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14906 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Dong Guo <guo.dong@intel.com>
Reviewed-by: Ni, Ruiyu <ruiyu.ni@intel.com>
Reviewed-by: Ouyang, Qian <qian.ouyang@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14905 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ni, Ruiyu <ruiyu.ni@intel.com>
Reviewed-by: Jin, Eric <eric.jin@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14904 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Eric Dong <eric.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14903 6f19259b-4bc3-4df7-8a09-765794883524
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config access protocol to get/set data with hii drivers.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14902 6f19259b-4bc3-4df7-8a09-765794883524
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priority order of option string/ prompt string/ text two string to highlight for a statement.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14901 6f19259b-4bc3-4df7-8a09-765794883524
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update other table version to refer to it. Remove the “/D TIANO_RELEASE_VERSION=0x00080006” option in Nt32Pkg DSC file, since it’s not used in source code.
Signed-off-by: Shumin Qiu <shumin.qiu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14900 6f19259b-4bc3-4df7-8a09-765794883524
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CpuExceptionHandlerLib is used.
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14899 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14898 6f19259b-4bc3-4df7-8a09-765794883524
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using HiiSetBrowserData/HiiGetBrowserData.
Signed-off-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Dong, Eric <eric.dong@intel.com>
Reviewed-by: Dong, Guo <guo.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14897 6f19259b-4bc3-4df7-8a09-765794883524
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defined as dynamic.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14896 6f19259b-4bc3-4df7-8a09-765794883524
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to find the storage.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14895 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14894 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14893 6f19259b-4bc3-4df7-8a09-765794883524
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Support values to match PCIe Base Spec rev 3.0
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chris Phillips <chrisp@hp.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14892 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chris Phillips <chrisp@hp.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14891 6f19259b-4bc3-4df7-8a09-765794883524
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BaseTools (r14889), FatPkg (r80).
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14890 6f19259b-4bc3-4df7-8a09-765794883524
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SS devices may have no response.
1.Port reset process may not be proper for some vendor's SS hubs. If the corresponding port shows the reset has been done by C_RESET bit we have to skip the whole reset process for attached devices.
2.Clean C_BH_RESET bit immediately to avoid usb timer entering too many times when 5 tiers hubs are connected.
3.Stop checking URB if there is an error happened.
4.Better error handling for fast hot-plug.
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Elvin Li <elvin.li@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14889 6f19259b-4bc3-4df7-8a09-765794883524
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