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2023-03-30UefiPayloadPkg: Support more input parameterLinus Wu1-1/+44
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4386 Add additional input parameter support --SpecRevision: user input spec version --Revision: user input revision --ProducerId: producer company name 1. UniversalPayloadBuild.py 2. Downgrade spec revision from 0.9 to 0.7 Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: Linus Wu <linusx.wu@intel.com>
2023-03-29OvmfPkg/CI: Boot OVMF in SMP mode.Gerd Hoffmann1-1/+1
Increase the chance that CI finds bugs in MP changes. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-29ArmVirtPkg: Fix depex in kvmtool guest Rtc librarySami Mujawar1-2/+2
The Rtc library for the kvmtool guest firmware configures the RTC controller address range as runtime memory by calling the gDS->SetMemorySpaceAttributes(). The SetMemorySpaceAttributes() function has a dependency on the CPU Arch Protocol. If the CPU Arch Protocol is not installed the call to set the memory attributes fails with error code EFI_NOT_AVAILABLE_YET. Therefore, set the library dependency on the CPU Arch protocol. Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-03-29ArmVirtPkg: Fix parsing of serial port nodeSami Mujawar1-2/+2
When scanning for the Serial Port in the device tree, the length and value parameters to ScanMem8() are not in the right order. This results in the serial port not being detected if the chosen node in the device tree has additional elements. Therefore, pass the parameters to ScanMem8() in the correct order to fix this issue. Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-03-29DynamicTablesPkg: Fix parsing of serial port nodeSami Mujawar1-2/+2
When scanning for the Serial Port in the device tree, the length and value parameters to ScanMem8() are not in the right order. This results in the serial port not being detected if the chosen node in the device tree has additional elements. Therefore, pass the parameters to ScanMem8() in the correct order to fix this issue. Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-03-29DynamicTablesPkg: Reduce log output from TableHelperLibSami Mujawar1-14/+14
Reduce the log output from Configuration Manager Object Parser in TableHelperLib by enabling the logs only if DEBUG_INFO is enabled. Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2023-03-29OvmfPkg: Use Xcode5 version of CpuExceptionHandlerLib for CLANGDWARFRebecca Cran1-1/+1
The CLANGDWARF toolchain has the same problem as XCODE5 linking CpuExceptionHandlerLib. So, use the Xcode5SecPeiCpuExceptionHandlerLib.inf when building with the CLANGDWARF toolchain. Since the difference is that the non-Xcode5 version uses `mov` while the Xcode5 version uses `lea`, they can be merged in future with the single version using `lea`. [ardb: the main difference is that the 'mov' instructions result in absolute symbol references, which are necessary because the code in question is copied in memory independently from the code that carries the symbols it refers to. The Xcode5 version has additional runtime handling to fix up the copied code with the correct absolute references.] Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
2023-03-29OvmfPkg: Replace static struct initialization with ZeroMem callRebecca Cran1-1/+3
Replace the static struct initialization with a call to ZeroMem to avoid generating a call to memset in certain build configurations. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-03-29RedfishPkg: fix config handler driver issuesNickle Wang2-6/+8
Bug fix: - function stack fault - config handler driver requires the dependency of Redfish Credential Protocol - incorrect caller id installation when failed to perform init() - fix typo Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
2023-03-29RedfishPkg: Redfish discover driver improvementNickle Wang3-57/+120
Bug fix: - function stack fault - properly handle "SubnetAddrInfoIPv6" when there is no IPv6 support - copy-n-paste error in RedfishGetHostInterfaceProtocolData() - fix typo Enhancement: - Redfish discover driver now can configure host IP address based on the information from SMBIOS type 42 record. This saves the effort of configuring host IP address in setup menu. - Performance improvement to driver binding process. Redfish discover driver will wait until all required drivers are ready and do driver binding start(). - Use CopyGuid() to copy GUID instead of intrinsic function. - Error handling when SMBIOS data is corrupted. Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
2023-03-29RedfishPkg/JsonLib: address coverity issueNickle Wang1-1/+2
Fix implicit conversion issue in JsonLib. Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
2023-03-28ArmVirtPkg: can't find gUefiOvmfPkgTokenSpaceGuidJianyong Wu1-0/+1
commit f13264b34 introduces a bug for CloudHv as OvmfPkg/OvmfPkg.dec is missing in CloudHvHasAcpiDtDxe.inf which leads to gUefiOvmfPkgTokenSpaceGuid found nowhere when build. Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
2023-03-28ArmPkg/SmbiosMiscDxe: Adjust the priority of getting firmware versionTinh Nguyen1-24/+38
The BIOS Firmware Version in the SMBIOS Type 0 can be fetched from the fixed PcdFirmwareVersionString or platform specific OemMiscLib. In fact, the support from OemMiscLib comes into play when the firmware version may be modified at boot time for extended information. Therefore, the priority of getting the version from OemMiscLib should be higher. In case there is no modification in the OemMiscLib, we have to keep HII string STR_MISC_BIOS_VERSION empty or 'Not Specified' to indicate that the firmware version should be fetched from the PcdFirmwareVersionString. Signed-off-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
2023-03-28OvmfPkg/PlatformInitLib: simplify mtrr setupGerd Hoffmann1-21/+15
With the new mmconfig location at 0xe0000000 above the 32-bit PCI MMIO window we don't have to special-case the mmconfig xbar any more. We'll just add a mtrr uncachable entry starting at MMIO window base and ending at 4GB. Update comments to match reality. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
2023-03-28OvmfPkg/PlatformInitLib: move mmconfig to 0xe0000000Gerd Hoffmann6-10/+10
Also swap the ordering of 32bit PCI MMIO window on q35, i.e. use the room between end of low memory and the start of the mmconfig bar. With a typical configuration on modern qemu with gigabyte-aligned memory the MMIO window start at 0x8000000, sized 1532 MB. In case there is memory present above 0x80000000 the window will start at 0xc0000000 instead, with 512 MB size. This depends on qemu commit 4a4418369d6d ("q35: fix mmconfig and PCI0._CRS"), so it raises the bar for the lowest supported version to qemu 4.1 (released Aug 2019). Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
2023-03-28OvmfPkg/PlatformInitLib: update address space layout commentGerd Hoffmann1-13/+15
Move the commment up so it is placed just before the address space calculations start. Also add q35 memory layout. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
2023-03-28OvmfPkg/RiscVVirt: Support multiple reserved memory rangesSunil V L1-77/+149
M-mode firmware ranges should not be used by EDK2/OS. Currently, we search for mmode_resv0 node in FDT and mark it as the reserved memory in EFI memory map. However, if there are multiple M-mode firmware ranges, then this will miss those extra ranges allowing the OS to access the memory and hit a fault. This issue is exposed since recent opensbi started creating two ranges for text and data. Fix this by searching for all reserved memory nodes and marking them as reserved in the EFI memory map. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
2023-03-27SecurityPkg/FvReportPei: Use FirmwareVolumeShadowPpiUmang Patel3-7/+32
If FirmwareVolumeShadow PPI is available, then use it to shadow FVs to memory. Otherwise fallback to CopyMem(). Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Patel Umang <umang.patel@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
2023-03-27MdeModulePkg/Include/Ppi: Add FirmwareVolumeShadowPpiUmang Patel2-0/+64
Add FirmwareVolumeShadow PPI to shadow an FV to memory. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Patel Umang <umang.patel@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Reduce the number of random testsDun Tan1-5/+5
Reduce the number of random tests. In previous patch, non-1:1 mapping is enbaled and it may need more than an hour and a half for the CI test, which may lead to CI timeout. Reduce the number of random test count to pass the CI. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE pagingDun Tan3-6/+11
Add RandomTest for PAE paging. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Enable PAE pagingDun Tan3-11/+73
Modify CpuPageTableLib code to enable PAE paging. In PageTableMap() API: When creating new PAE page table, after creating page table, set all MustBeZero fields of 4 PDPTE to 0. The MustBeZero fields are treated as RW and other attributes by the common map logic. So they might be set to 1. When updating exsiting PAE page table, the special steps are: 1.Prepare 4K-aligned 32bytes memory in stack for 4 temp PDPTE. 2.Copy original 4 PDPTE to the 4 temp PDPTE and set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. 4.After updating the page table, set the MustBeZero fields of 4 temp PDPTE to 0. 5.Copy the temp PDPTE to original PDPTE. In PageTableParse() API, also create 4 temp PDPTE in stack. Copy original 4 PDPTE to the 4 temp PDPTE. Then set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. Finally use the address of temp PDPTE as the page table address. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg: Combine branch for non-present and leaf ParentEntryDun Tan1-53/+32
Combine 'if' condition branch for non-present and leaf Parent Entry in PageTableLibMapInLevel. Most steps of these two condition are the same. This commit doesn't change any functionality. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Add check for page table creationDun Tan1-0/+10
Add code to compare ParentPagingEntry Attribute&Mask and input Attribute&Mask to decide if new next level page table is needed in non-present ParentPagingEntry condition. This can help avoid unneccessary page table creation. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we only want to map [1G, 1G+2M] linear address still as non-present. The expected behaviour should be nothing happens in the process. However, previous code logic doesn't check if ParentPagingEntry Attribute&Mask and input Attribute&Mask are the same in non-present ParentPagingEntry condition. Then a new 4K memory is allocated for Lv2 since 1G+2M is not 1G-aligned. So when ParentPagingEntry is non-present, before allocate 4K memory for next level paging, we also check if ParentPagingEntry Attribute& Mask and input Attribute&Mask are the same. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg: Modify UnitTest code since tested API is changedZhiguang Liu3-59/+67
Last commit changed the CpuPageTableLib API PageTableMap, unit test code should also be modified. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2023-03-27UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.infZhiguang Liu3-89/+90
The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit field PageTableBaseAddress is from bit 12 to bit 52. This means if the compiler treats the 64bits value as two UINT32 value, the field PageTableBaseAddress spans two UINT32 value. That's why when building in NOOPT mode in IA32, the below issue is noticed: unresolved external symbol __allshl This patch fix the build failure by seperate field PageTableBaseAddress into two fields, make sure no field spans two UINT32 value. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModifiedDun Tan1-12/+33
Modify RandomTest to check if parameter IsModified of PageTableMap() correctlly indicates whether input page table is modified or not. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter.Dun Tan5-46/+88
Add OUTPUT IsModified parameter in PageTableMap() to indicate if page table has been modified. With this parameter, caller can know if need to call FlushTlb when the page table is in CR3. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random testDun Tan1-4/+4
Enable non-1:1 mapping in random test. In previous test, non-1:1 test will fail due to the non-1:1 mapping issue in CpuPageTableLib and invalid Input Mask when creating new page table or mapping not-present range. Now these issue have been fixed. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/AttrDun Tan2-26/+133
Modify RandomTest to check invalid input. When creating new page table or updating exsiting page table: 1.If set [LinearAddress, LinearAddress+Length] to non-present, all other attributes should not be provided. 2.If [LinearAddress, LinearAddress+Length] contain non-present range, the Returnstatus of PageTableMap() should be InvalidParameter when: 2.1Some of attributes are not provided when mapping non-present range to present. 2.2Set any other attribute without setting the non-present range to Present. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Add LastMapEntry pointerDun Tan1-8/+10
Add LastMapEntry pointer to replace MapEntrys->Maps[MapsIndex] in SingleMapEntryTest () of RandomTest. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTestDun Tan1-22/+21
Add an input parameter to control the probability of returning true. Change RandomBoolean() in RandomTest from 50% chance returning true to returning true with the percentage of input Probability. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and AttrDun Tan1-2/+127
Add manual test case to check input Mask and Attribute. The check steps are: 1.Create Page table to cover [0, 2G]. All fields of MapMask should be set. 2.Update Page table to set [2G - 8K,2G] from present to non-present. All fields of MapMask except present should not be set. 3.Still set [2G - 8K, 2G] as not present, this case is permitted. But set [2G - 8K, 2G] as RW is not permitted. 4.Update Page table to set [2G - 8K, 2G] as present and RW. All fields of MapMask should be set. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib:Add check for Mask and AttrDun Tan2-1/+86
For different usage, check if the combination for Mask and Attr is valid when creating or updating page table. 1.For non-present range 1.1Mask.Present is 0 but some other attributes is provided. This case is invalid. 1.2Mask.Present is 1 and Attr.Present is 0. In this case,all other attributes should not be provided. 1.3Mask.Present is 1 and Attr.Present is 1. In this case,all attributes should be provided to intialize the attribute. 2.For present range 2.1Mask.Present is 1 and Attr.Present is 0.In this case, all other attributes should not be provided. All other usage for present range is permitted. In the mentioned cases, 1.2 and 2.1 can be merged into 1 check. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/MpInitLib: Add code to initialize MapMaskDun Tan1-4/+1
In function CreatePageTable(), add code to initialize MapMask to MAX_UINT64. When creating new page table or map non-present range to present, all attributes should be provided. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entryDun Tan1-8/+11
When splitting leaf parent entry to smaller granularity, create child page table before modifing parent entry. In previous code logic, when splitting a leaf parent entry, parent entry will point to a null 4k memory before child page table is created in this 4k memory. When the page table to be modified is the page table in CR3, if the executed CpuPageTableLib code is in the range mapped by the modified leaf parent entry, then issue will happen. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leafDun Tan1-1/+2
Clear PageSize bit(Bit7) for non-leaf entry in PageTableLibSetPnle. This function is used to set non-leaf entry attributes so it should make sure that the PageSize bit of the entry should be 0. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issueDun Tan1-1/+11
In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginningDun Tan1-9/+12
Move some local variable initialization to the beginning of the function. Also delete duplicated calculation for RegionLength. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Add check for input LengthDun Tan2-3/+7
Add check for input Length in PageTableMap (). Return RETURN_SUCCESS when input Length is 0. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' conditionDun Tan1-10/+1
Remove unneeded 'if' condition in CpuPageTableLib code. The deleted code is in the code branch for present non-leaf parent entry. So the 'if' check for (ParentPagingEntry->Pnle.Bits.Present == 0) is always FALSE. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2023-03-27PcAtChipsetPkg: Add PCD for RTC default yearMichael D Kinney4-2/+13
Add PcdRtcDefaultYear to specify the default year to use when the RTC is in an invalid state. Make sure PcdRtcDefaultYear is >= PcdMinimalValidYear and <= PcdMaximalValidYear. Set the default value for this PCD to PcdMinimalValidYear to preserve the existing behavior. A platform DSC file can override this default value setting. Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2023-03-27UefiCpuPkg: Solve that stack top address is not mapped in pagetableXie, Yuanhao1-0/+1
For the case CPU logic index is 0, RSP points to the very top of all AP stacks. That address is not mapped in page table. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2023-03-27UefiPayloadPkg: Add gUefiAcpiBoardInfoGuid supportGua Guo1-3/+6
if system both exist gUefiAcpiBoardInfoGuid and rsdp, we may need to use gUefiAcpiBoardInfoGuid as final config to have backward support. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Reviewed-by: James Lu <james.lu@intel.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
2023-03-26MdePkg/Include: Add IPMI KCS definitionsAbner Chang2-0/+82
BZ #4354 This change adds definitions for IPMI KCS. Spec ref: https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Acked-by: Isaac Oram <isaac.w.oram@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com>
2023-03-26MdePkg/Include: Add DMTF MCTP definitionsAbner Chang1-0/+139
BZ #4355 This change adds definitions for DMTF MCTP base specification. Spec ref: https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1.3.1.pdf Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Acked-by: Isaac Oram <isaac.w.oram@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-03-26MdePkg/Include/Ppi: Remove Itanium leftover data structurePaweł Poławski1-46/+5
Itanium support has been removed from EDK2 around 2019. ITANIUM_HANDOFF_STATUS data structure looks to be some leftover from that process. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1560 GitHub: https://github.com/tianocore/edk2/commit/4e1daa60f5372c22a11503961061ffa569eaf873 There is also positive side effect of this data structure removal. Due to HOB allocation type used in PEI stage there is a limit how much data about virtual CPU can be hold. This limit result in only 1024 vCPU can be used by VM. With Itanium related data structure removed more allocated space can be used for vCPU data and with current allocation limit will change from 1024 to around 8k vCPUs. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Paweł Poławski <ppolawsk@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-03-24IntelFsp2Pkg: Fix NASM X64 build warnings.Chasel Chiu2-11/+9
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377 Fix below warnings generated by NASM X64 build: /X64/FspHelper.iii:26: warning: signed dword value exceeds bounds /X64/FspHelper.iii:35: warning: signed dword value exceeds bounds /X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds Also replaced "cmp reg, 0" with "test reg, reg" per optimization suggestion. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2023-03-24BaseTools: Replace duplicate __PcdSet prototype with __PcdGetRebecca Cran1-7/+6
Replace the duplicate __PcdSet prototype in PcdValueCommon.h with the prototype for __PcdGet. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2023-03-24BaseTools: Source/C/Common: Fix doc block locations and convert to DoxygenRebecca Cran29-4065/+2072
Move the documentation blocks from between the parameter list and function body to above the function. Convert all the documentation blocks to Doxygen format. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
generated by cgit v1.1 at 2024-09-17 20:49:33 +0000