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2016-09-14UefiCpuPkg/SecCore: Abstract worker function GetBistFromHob()Jeff Fan1-20/+61
Abstract one worker function to get CPU BIST from the GUIDed-HOB. Add SecPlatformInformationBist() and SecPlatformInformation2Bist() to invoke GetBistFromHob(). Add in/out for parameter in function header. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/SecCore: Add SecBist.cJeff Fan4-2/+152
Add SecBist.c and copy GetBistInfoFromPpi() and SecPlatformInformation2() from UefiCpuPkg/CpuMpPei/CpuBist.c. And update SecMain.c, SecMain.inf and UefiCpuPkg.dsc accordinlgy to pass build. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/CpuMpPei: Build GUIDed-HOB to store all CPU BIST DataJeff Fan3-23/+46
Build gEfiSecPlatformInformation2PpiGuid GUIDed-HOB to store all CPU BIST data that could be used not only by SecPlatformInformation2(), but also by CPU MP Dxe driver to get CPU BIST data. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/CpuMpPei: Fix BistData ouput errorJeff Fan1-1/+1
ProcessorInfo.ProcessorId is UINT64 type even it's valid value is UINT32. Use %x only output the low 4 bytes and keep the high 4 bytes in stack that will be output as the second parameter BistData. Typecast ProcessorInfo.ProcessorId to UINT32 could make BistData output correctly. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/CpuMpPei: Add parameter BistInformationSizeJeff Fan1-3/+10
Add one OPTIONAL parameter BistInformationSize for GetBistInfoFromPpi(). Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/CpuDxe: Fix duplicated status code reportJeff Fan1-14/+15
If CPU Bist data is not zero, we will report Status code. But there is one bug that will report each processor's status code duplicated with NumberOfData times. This fix is to exchange the loop order on NumberOfData and mNumberOfProcessors. It could make sure the report status code only once for each processor. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-13MdePkg/BaseMemoryLibOptDxe ARM|AARCH64: disallow use in SEC & PEI phasesArd Biesheuvel1-0/+9
The new accelerated ARM and AARCH64 implementations take advantage of features that are only available when the MMU and Dcache are on. So restrict the use of this library to the DXE phase or later. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-09-13MdePkg/BaseMemoryLibOptDxe: add accelerated AARCH64 routinesArd Biesheuvel5-1/+839
This adds AARCH64 support to BaseMemoryLibOptDxe, based on the cortex-strings library. All string routines are accelerated except ScanMem16, ScanMem32, ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few occurrences exist in the codebase) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-09-13MdePkg/BaseMemoryLibOptDxe: add accelerated ARM routinesArd Biesheuvel10-14/+1209
This adds ARM support to BaseMemoryLibOptDxe, partially based on the cortex-strings library (ScanMem) and the existing CopyMem() implementation from BaseMemoryLibStm in ArmPkg. All string routines are accelerated except ScanMem16, ScanMem32, ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few occurrences exist in the codebase) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-09-13MdePkg/BaseMemoryLib: widen aligned accesses to 32 or 64 bitsArd Biesheuvel3-14/+140
Since the default BaseMemoryLib should be callable from any context, including ones where unaligned accesses are not allowed, it implements InternalCopyMem() and InternalSetMem() using byte accesses only. However, especially in a context where the MMU is off, such narrow accesses may be disproportionately costly, and so if the size and alignment of the access allow it, use 32-bit or even 64-bit loads and stores (the latter may be beneficial even on a 32-bit architectures like ARM, which has load pair/store pair instructions) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-09-13ArmVirtPkg/FdtParser: avoid unaligned accesses with the MMU offArd Biesheuvel2-16/+12
When parsing the device tree to find the memory node, we are still running with the MMU off, which means unaligned memory accesses are not allowed. Since the FDT only mandates 32-bit alignment, 64-bit quantities are not guaranteed to appear naturally aligned, and so should be accessed using 32-bit accesses instead. Reported-by: Julien Grall <julien.grall@arm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-09-13ArmPkg/ArmMmuLib: base page table VA size on GCD memory map sizeArd Biesheuvel3-12/+10
As reported by Eugene, the practice of sizing the address space in the virtual memory system based on the maximum address in the table passed to ArmConfigureMmu() is problematic, since it fails to take into account the fact that the GCD memory space may be extended at a later time, both for memory and for MMIO. So instead, choose the VA size identical to the GCD memory map size, which is based on PcdPrePiCpuMemorySize on ARM systems. Reported-by: Eugene Cohen <eugene@hp.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-13ArmPkg/ArmMmuLib: use a pool allocation for the root tableArd Biesheuvel1-5/+22
Currently, we allocate a full page for the root translation table, even if the configured translation only requires two entries (16 bytes) for the root level, which happens to be the case for a 40 bit VA. Likewise, for a 36-bit VA space, the root table only needs 16 entries of 8 bytes each, adding up to 128 bytes. So switch to a pool allocation for the root table if we can, but take into account that the architecture requires it to be naturally aligned to its size, i.e., a 64 byte table requires 64 byte alignment, whereas pool allocations in general are only guaranteed to be aligned to 8 bytes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-13ArmPkg/ArmMmuLib: remove bogus alignment of page allocationsArd Biesheuvel1-6/+4
In commit 7d189f99d81c ("ArmPkg/Mmu: Fix bug of aligning new allocated page table"), we fixed a flaw in the logic regarding alignment of newly allocated translation table pages. However, we all failed to spot that aligning page based allocations to page size is rather pointless to begin with, so simply allocate a single page each time we add new pages to the translation tables. Also, drop the unnecessary cast. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-13ArmPkg/ArmMmuLib: deobfuscate GetRootTranslationTableInfo ()Ard Biesheuvel1-31/+4
The relations between T0SZ, the number of translation levels and the size/alignment of the root table can be expressed in simple arithmetic expressions, so get rid of the lookup table. Note that this disregards the fact that the maximum value of T0SZ is 39 not 42 (as one would expect for the smallest VA size using 2 levels) but since this corresponds to a VA size of 32 MB and 4 MB, respectively, neither of which are sufficient to run UEFI, we can safely ignore the distinction. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-13OvmfPkg: Fix typing errors in header filesThomas Huth7-9/+9
Correct some typos in the header files of the OvmfPkg (which have been discovered with the codespell utility). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-09-12OvmfPkg: Fix typing errorsThomas Huth9-14/+14
Correct some typos (discovered with the codespell utility) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Thomas Huth <thuth@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-09-12OvmfPkg: convert C files with LF line terminators to CRLFLaszlo Ersek5-805/+805
Run "unix2dos" on the affected files. "git show -b" produces no diff for this patch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Thomas Huth <thuth@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2016-09-12OvmfPkg/IndustryStandard: make "Xen/grant_table.h" pure ASCIILaszlo Ersek1-1/+1
The header file includes the UTF-8 encoding (0xE2 0x80 0x99) of the U+2019 (RIGHT SINGLE QUOTATION MARK) code point. Replace it with a simple apostrophe (U+0027, ASCII 0x27). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Thomas Huth <thuth@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2016-09-12MdeModulePkg/HiiDB: Handle the "&READONLY" tag in <KeywordResp> correctlyDandan Bi1-4/+13
This patch is to fix the incorrect logic when handling the "&READONLY" tag in <KeywordResp>. 1. In UEFI spec, the "&READONLY" tag is in upper case, but using the lower case in current codes by mistake. 2. The logic in checking the ReadOnly flag is not correct. Whether having "&READONLY" tag must be consistent with the result of "ExtractReadOnlyFromOpCode" function. Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-09-12MdeModulePkg/UiApp: Fix incorrect question idDandan Bi1-1/+2
For a question, its question id can not be zero. This patch is to fix the issue that using zero as question id. Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-09-12Nt32Pkg: Fix VS2010/VS2012 build failureDandan Bi1-0/+2
Initialize the variable "OptionNumber". Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-09-09OptionRomPkg: .dsc fixes for ARM/AARCH64 and USB driversLeif Lindholm1-1/+10
Drivers under OptionRomPkg wouldn't build standalone, since ARM and AARCH64 were missing from SUPPORTED_ARCHITECTURES. So add them. Also, add some compiler libraries needed for ARM/AARCH64 GCC toolchains (CompilerIntrinsicsLib and BaseSwStackCheckLib). Also, the UsbNetworking drivers were not listed under [Components], so failed to build standalone. This patch adds them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-09-09ArmPkg/ArmGicLib: use correct loop variableArd Biesheuvel1-1/+1
The ArmGicLib API function GicGetCpuRedistributorBase () declares GicCpuRedistributorBase to iterate over the redistributors of all CPUs, but then inadvertently advances GicRedistributorBase instead. Reported-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-09ArmPkg/DefaultExceptionHandlerLib: trim module name in backtrace outputArd Biesheuvel1-3/+23
As reported by Vishal, the new backtrace output would be more useful if it did not contain the full absolute path of each module in the list. So strip off everything up to the last forward slash or backslash in the string. Example output: IRQ Exception at 0x000000005EF110E0 DxeCore.dll loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EF121F0) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EF1289C) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEFB6B4) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEFAA44) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEFB450) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEF938C) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEF8D04) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEFA8E8) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEF3C14) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEF3E48) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EF0C838) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEEF70C) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEEE93C) loaded at 0x000000005EEED000 called from DxeCore.dll (0x000000005EEEE024) loaded at 0x000000005EEED000 Suggested-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-09ArmPlatformPkg/NorFlashDxe: use strictly aligned CopyMem()Ard Biesheuvel1-2/+61
The UEFI spec stipulates that unaligned accesses should be enabled on CPUs that support them, which means all of them, given that we no longer support pre-v7 ARM cores, and the AARCH64 bindings mandate support for unaligned accesses unconditionally. This means that one should not assume that CopyMem () is safe to call on regions that may be mapped using device attributes, which is the case for the NOR flash. Since we have no control over the mappings when running under the OS, and given that write accesses require device mappings, we should not call CopyMem () in the read path either, but use our own implementation that is guaranteed to take alignment into account. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-09MdePkg/BaseLib AARCH64: terminate stack frame list on stack switchArd Biesheuvel1-0/+1
When switching to the DXE phase stack, set the frame pointer to zero so that code walking the stack frame will not try to access stack frames belonging to the old stack. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-09BaseTools/EfiRom: supply missing machine type lookup stringsLaszlo Ersek1-0/+3
"EfiRom --dump" does not recognize the 0x8664 machine type: > EFI ROM header contents > EFI Signature 0x0EF1 > Compression Type 0x0001 (compressed) > Machine type 0x8664 (unknown) > Subsystem 0x000B (EFI boot service driver) > EFI image offset 0x0050 (@0xF650) Add lookup strings for the remaining EFI_IMAGE_MACHINE_* numeric macros that can be found in "BaseTools/Source/C/Include/IndustryStandard/PeImage.h". The strings follow Table 12. "UEFI Image Types" from the UEFI v2.6 spec. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-09-08ShellPkg/UefiHandleParsingLib: fix retval for empty child controller arrayLaszlo Ersek1-2/+9
The ParseHandleDatabaseForChildControllers() function intends to work like this: (1) It allocates a "HandleBufferForReturn" local array that's guaranteed to be big enough for all found handles, (2) it collects the handles, both counting them in the (mandatory) "MatchingHandleCount" output parameter, and saving them in the local "HandleBufferForReturn" array, (3) if the caller is not interested in the actual handles, then "HandleBufferForReturn" is released, (4) if the caller is interested in the handles, and we've found some, then "HandleBufferForReturn" is passed out through the "MatchingHandleBuffer" output parameter, (5) if the caller is interested in the actual handles, but we've found none, then the "MatchingHandleBuffer" output parameter is set to NULL. The ASSERT() at the end of the function makes this clear, but the implementation does not conform to (5). Fix it. Cc: Jaben Carsey <jaben.carsey@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Tapan Shah <tapandshah@hpe.com> Reported-by: Tapan Shah <tapandshah@hpe.com> Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=112 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Tapan Shah <tapandshah@hpe.com>
2016-09-08ShellPkg/UefiHandleParsingLib: fix IN/OUT notation in child ctrlr parsingLaszlo Ersek2-4/+4
"MatchingHandleCount" is an output parameter of ParseHandleDatabaseForChildControllers(). Cc: Jaben Carsey <jaben.carsey@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Tapan Shah <tapandshah@hpe.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Tapan Shah <tapandshah@hpe.com>
2016-09-08ShellPkg: pci -i -_e to print next capabilityAbdul Lateef Attar1-2/+2
According to PCI spec the next AER capability is relative to the beginning of PCI configuration space. Hence substract the base offset to get the next capability. "-_e" option is changed from TypeFlag to TypeValue, so that user can specify individual AER capability to print. e.g. pci 00 00 01 -i -_e <capability-id> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abdul Lateef Attar <abdul-lateef.attar@hpe.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
2016-09-08ArmPkg/ArmBaseLib: clean up directory structureArd Biesheuvel15-12/+12
For historical reasons, the files under ArmLib are split up into 'common' files under Common/, containing common C files as well as AArch64 and Arm specific asm files, and ArmV7 and AArch64 files under ArmV7/ and AArch64/, respectively. This presumably dates back to the time when ArmLib supported different revisions of the 32-bit architecture (i.e., pre-V7) Since the PI spec requires V7 or later, we can simplify this to Arm/ and AArch64, which aligns ArmLib with the majority of other modules that carry ARM or AArch64 specific code. So move the files around so that shared files live at the same level as ArmBaseLib.inf, and ARM/AArch64 specific files live in Arm/ or AArch64/, respectively. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08ArmPkg/ArmBaseLib: remove MemoryAllocationLib.h includesArd Biesheuvel2-2/+0
The ArmBaseLib timer code does not depend on MemoryAllocationLib at all, so remove the #includes referring to it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08Maintainers.txt: Add Giri as IntelFsp2*Pkg, IntelSiliconPkg maintainerJiewen Yao1-0/+3
Add Giri as 2nd maintainer to IntelFsp2*Pkg and IntelSiliconPkg. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Amy Chan <amy.chan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08ArmPlatformPkg: remove EFI_MEMORY_UC attribute from normal memoryArd Biesheuvel3-3/+0
On ARM systems, mapping normal memory as device memory may have unintended side effects, given that unaligned accesses or loads and stores with special semantics (e.g., load/store exclusive) may fault or may not work as expected. Similarly, DC ZVA instructions are only supported on normal memory, not device memory. So remove the EFI_MEMORY_UC attribute that we set by default on system RAM. If any region requires this attribute, it is up to the driver to set this attribute, and to ensure that no offending operations are performed on it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08ArmVirtPkg: restrict mapping attributes of normal memory to EFI_MEMORY_WBArd Biesheuvel2-5/+1
In general, on an ARM system, mapping normal memory as device memory may have unintended side effects, given that unaligned accesses or loads and stores with special semantics (e.g., load/store exclusive) may fault or may not work as expected. Under KVM, the situation is even worse, since the host may not expect the guest to perform uncached accesses, and so writes to such an uncached region may get lost completely. Since the only safe mapping type under KVM is EFI_MEMORY_WB, remove all other memory type attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-09-08ArmPkg/ArmLib: remove all ArmLib flavors except ArmBaseLibArd Biesheuvel9-405/+0
This removes the following ArmLib implementation, which were, apart from the fact that they targeted either ARM or AARCH64, fully identical: ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf ArmPkg/Library/ArmLib/AArch64/AArch64LibPei.inf ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf Only ArmBaseLib remains, which can fulfil the dependencies upon each of the listed flavors. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08ArmVirtPkg: replace all ArmLib resolutions with ArmBaseLibArd Biesheuvel3-24/+3
The various ArmLib flavors are identical in practice, and a new ArmBaseLib has been introduced that can replace all of them. So replace all occurrences with ArmBaseLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-09-08BeagleBoardPkg EmbeddedPkg Omap35xxPkg: move to ArmBaseLibArd Biesheuvel3-10/+3
The various ArmLib flavors are identical in practice, and a new ArmBaseLib has been introduced that can replace all of them. So replace all occurrences with ArmBaseLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08ArmPkg/ArmLib: introduce ArmBaseLibArd Biesheuvel2-0/+60
Introduce a new ArmLib version ArmBaseLib, which encapsulates the ARM version ArmV7Lib and the AArch64 version AArch64Lib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08ArmPkg/ArmLib: remove NullArmLibArd Biesheuvel3-159/+0
Remove the NULL instance of ArmLib: it is not currently used, and its usefulness its dubious. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-upDennis Chen9-27/+27
According to the ACPI 6.0/6.1 spec, the physical base address of GICC, GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC base address PCDs to 64-bit, and fix up all users. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Dennis Chen <dennis.chen@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-09-08OvmfPkg/QemuBootOrderLib: drop too strict "/HD(" suffix from vblk prefixLaszlo Ersek1-5/+5
Translating QEMU's virtio-block OpenFirmware device path to a UEFI device path prefix was one of the earliest case handled in QemuBootOrderLib. At that time, I terminated the translation output (the UEFI devpath prefix) with a "/HD(" suffix. The intent was for the translation to prefix-match only boot options with HD() device path nodes in them, that is, no auto-generated "device level" boot options. This was motivated by prioritizing specific boot options created by OS installers over auto-generated "device level" options. However, practice has shown that: - OS installers place their installed boot options first in the boot order anyway, - other device types (SATA disks, virtio-scsi disks), where "/HD(" is not appended, work just fine, - requiring "/HD(" actually causes problems: after the OS-installed specific boot option has been lost (or purposely removed), the auto-generated "device level" boot option does the right thing (see the Default Boot Behavior under <http://blog.uncooperative.org/blog/2014/02/06/the-efi-system-partition/>). The "/HD(" requirement causes such boot options to be dropped, which prevents "fallback.efi" from running. Relax the matching by removing the "/HD(" suffix from the translated prefix. Cc: Jordan Justen <jordan.l.justen@intel.com> Fixes: e06a4cd134064590aa1a855ff4b973023279e805 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1373812 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-09-08BaseTools VfrCompile Pccts: Update GCC Flags to the specific one with BUILD_ ā†µLiming Gao2-12/+19
prefix This change is also applied to VfrCompile Pccts antlr and dlg tool. In V2, add the missing C rules. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-09-08BaseTools VfrCompile GNU makefile: Replace CXX with BUILD_CXXLiming Gao1-5/+5
The change is missing in VfrComile GNUmakefile. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-09-08BaseTools GNU makefile: remove unused .S ruleLiming Gao1-3/+0
Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-09-08BaseTools GNU makefile: Add BUILD_CXXFLAGS to align make built-in ruleLiming Gao2-1/+2
GNU make built-in rule to Compiling C++ programs with ā€˜$(CXX) $(CPPFLAGS) $(CXXFLAGS) -cā€™. To align to it, add empty BUILD_CXXFLAGS in cpp rule. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-09-08UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in commentJeff Fan1-0/+51
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/XeonE7Msr.h: add MSR reference from SDM in commentJeff Fan1-0/+31
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/XeonDMsr.h: add MSR reference from SDM in commentJeff Fan1-0/+106
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
generated by cgit v1.1 at 2024-08-01 09:22:54 +0000