| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
On macOS, /usr/bin/gcc is clang, and so doesn't have
the -Wno-error=stringop-overflow flag that was added
for gcc 12.
Update the GNUmakefile for DevicePath to skip setting
that on macOS.
Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
|
|
This reverts commit 039bdb4d3e96f9c9264abf135b8a0eef2e2b4860 for tag202208.
This brings the behavior changes, and needs more discussion.
Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Bob Feng <bob.c.feng@intel.com>
|
|
This reverts commit d5fd86f256b9ab5b4e3aff70d3c177c18faea892 for tag202208.
This feature will be merged after stable tag 202208 is created.
Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
|
|
This reverts commit 2812668bfc121ee792cf3302195176ef4a2ad0bc for tag202208.
This feature will be merged after stable tag 202208 is created.
Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
|
|
Update package maintainers for below package/arch,
1. RISCV64 Architecture:
Abner is stepping out from RISC-V stuff for now and hand over edk2 RISC-V
responsibilities to Sunil.
Daniel Schaefer is no longer with HPE. Update his email address for
RISCV64 arch. He will keep helping on RISC-V stuff with his personal
email.
2. EmbeddedPkg:
Daniel Schaefer is no longer with HPE. Update his email address for
EmbeddedPkg.
3. EmulatorPkg and RedfishPkg:
Nickle Wang is no longer with HPE. Update his email address for
EmulatorPkg and RedfishPkg packages. He will use the personal email for
the time being until he gets ready with his next journey.
Signed-off-by: Abner Chang <abner.chang@amd.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Nickle Wang <nickle@csie.io>
Reviewed-by: Daniel Schaefer <git@danielschaefer.me>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Nickle Wang <nickle@csie.io>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
|
|
Bugzilla: 3995 (https://bugzilla.tianocore.org/show_bug.cgi?id=3995)
ACPI 6.4 spec states that if the revision field in the DSDT header is less
than 2, then all integers are restricted in width to 32 bits, including in
SSDTs.
Arm Base boot requirements state that platforms must conform to ACPI 6.3
or later, and that legacy tables are not supported.
Adds a check for this field and raise warning if revision is less
than 2 on arm.
Signed-off-by: Edward Pickup <edward.pickup@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
|
|
https://bugzilla.tianocore.org/show_bug.cgi?id=4018
Coverity report FORWARD_NULL and OVERFLOW_BEFORE_WIDEN potential defect
in UefiPayloadPkg.
Signed-off-by: Gregx Yeh <gregx.yeh@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: James Lu <james.lu@intel.com>
|
|
There is no function to send POST request with the
ContentType different from "application\json".
There is no function to send DELETE request with the body.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Signed-off-by: Igor Kulchytskyy <igork@ami.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
|
|
Definitions of the required functions to send requests to BMC
are in the PrivateInclude folder. So they cannot be used by
the other Redfish packages.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Signed-off-by: Igor Kulchytskyy <igork@ami.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
|
|
Host Interface details are described by the SMBIOS Type 42
table. The table is published by the RedfishHostInterfaceDxe
driver. That driver supports PCI-E and USB host interface
types.The table is consumed by the edfishGetHostInterfaceProtocolData
function in the RedfishDiscoverDxe driver. The function only supports
PCI-E host interface type.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Signed-off-by: Igor Kulchytskyy <igork@ami.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
|
|
Add NVME_ENABLE macro to control NvmExpressDxe driver.
Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Gua Guo <gua.guo@intel.com>
Signed-off-by: Kavya <k.kavyax.sravanthi@intel.com>
|
|
Return PciRootBridges instead of NULL and set
PcdPciDisableBusEnumeration to FALSE when
root bridge count is zero.
Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Gua Guo <gua.guo@intel.com>
Signed-off-by: Kavya <k.kavyax.sravanthi@intel.com>
|
|
Parse Type 0 or Local APIC structure.
Also parse the Local APIC Flags as bitfields.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
|
|
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4021
When the size of a EFI_SECTION_FREEFORM_SUBTYPE_GUID section required
the use of EFI_FREEFORM_SUBTYPE_GUID_SECTION2 header, set the section
type to EFI_SECTION_FREEFORM_SUBTYPE_GUID.
Cc: Leif Lindholm <llindhol@qti.qualcomm.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Konstantin Aladyshev <aladyshev22@gmail.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Leif Lindholm <llindhol@qti.qualcomm.com>
|
|
Updated SmBios.h with new fields added as part of SMBIOS 3.6.0 spec update.
Signed-off-by: Sainadh Nagolu <sainadhn@ami.com>
Cc: Vasudevan Sambandan <vasudevans@ami.com>
Cc: Sundaresan S <sundaresans@ami.com>
Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
|
|
Since PeerGroups has a variable number of entries, new fields added
after PeerGroups are defined in a extended structure.
Done changes in PrintInfo.c to access those fields using
SMBIOS_TABLE_TYPE9_EXTENDED structure from SmBios.h.
Signed-off-by: Sainadh Nagolu <sainadhn@ami.com>
Cc: Vasudevan Sambandan <vasudevans@ami.com>
Cc: Sundaresan S <sundaresans@ami.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
|
|
In Type9 structure since PeerGroups has a variable
number of entries, must not define new fields in the structure.So added an
extended structure and defined new fields added after PeerGroups. Also done
some improvements to Smbios 3.5.0 spec changes.
Signed-off-by: Sainadh Nagolu <sainadhn@ami.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
|
|
Some print statements use format specifiers like %N/%H/%E/%B that are
only supported in the shell print functions. In the ordinary 'Print'
function they are just displayed as letters N/H/E/B.
Remove these unsupported format specifiers from the 'Print' statements
to fix the issue.
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
|
|
The current implementation does not check if Language or DriverName
are NULL. This causes the SCT test suite to crash.
Add a check to return EFI_INVALID_PARAMETER if any of these pointers
are NULL.
Signed-off-by: Dimitrije Pavlov <Dimitrije.Pavlov@arm.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
|
|
The current implementation does not check if Info or SizeInfo
pointers are NULL. This causes the SCT test suite to crash.
Add a check to return EFI_INVALID_PARAMETER if any of these
pointers are NULL.
Signed-off-by: Dimitrije Pavlov <Dimitrije.Pavlov@arm.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
|
|
The current implementation does not check if Progress or Results
pointers in ExtractConfig are NULL, or if Progress pointer in
RouteConfig is NULL. This causes the SCT test suite to crash.
Add a check to return EFI_INVALID_PARAMETER if any of these pointers
are NULL.
Signed-off-by: Dimitrije Pavlov <Dimitrije.Pavlov@arm.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
|
|
Add host based unit tests for the CpuPageTableLib services.
Unit test focuses on PageTableMap function, containing two kinds of test
cases: manual test case and random test case.
Manual test case creates some corner case to test function PageTableMap.
Random test case generates multiple random memory entries (with random
attribute) as the input of function PageTableMap to get the output
pagetable. Output pagetable will be validated and be parsed to get output
memory entries, and then the input and output memory entries will be
compared to verify the functionality.
The unit test is not perfect yet. There are options for random test, and
some of them control the test coverage, and some option are not ready.
Will enhance in the future.
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
|
|
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4013
For the SMBIOS version can be update by UPL,we create
the gUniversalPayloadSmbios3TableGuid HOB to store
the value then updated version.
Cc: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: James Lu <james.lu@intel.com>
Reviewed-by: Gua Guo <gua.guo@intel.com>
Signed-off-by: KasimX Liu <kasimx.liu@intel.com>
|
|
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4019
FSPM_ARCH2_UPD in FspApiEntryM.nasm was not up-to-date and
should be fixed for both IA32 and X64 builds.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
|
|
Remove clearing CR0.WP when marking the memory used for page table
as read-only in the page table itself created by UefiPayloadEntry.
This page table address is written to Cr3 after these protection
steps. Till this, the memory used for page table is always RW.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Ray Ni <ray.ni@intel.com>
|
|
Remove clearing CR0.WP when marking the memory used for page table
as read-only in the page table itself created by DxeIpl. This page
table address is written to Cr3 after these protection steps. Till
this, the memory used for page table is always RW.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Ray Ni <ray.ni@intel.com>
|
|
This patch is code refactoring and doesn't change any functionality.
Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. In previous
code, mInternalCr3 is used to pass address of page table which is
different from Cr3 register in different level of SetMemoryAttributes
function. Now remove it and pass the page table base address from the
root function parameter to simplify the code logic.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
|
|
This patch is code refactoring and doesn't change any functionality.
Add a new mIsShadowStack flag to identify whether current memory is
shadow stack. Previous smm code logic regards a RO range as shadow
stack and set the dirty bit in corresponding page table entry if
mInternalCr3 is not 0, which may be confusing.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
|
|
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4014
If Configured Memory Speed is 65,535 MT/s or greater,
and the actual speed is stored in the Extended Configured Memory Speed
field. but current Smbiosview have no this logic.
Signed-off-by: Shengfengx Xue <shengfengx.xue@intel.com>
|
|
Ref:https://bugzilla.tianocore.org/show_bug.cgi?id=4000
Change flow to bus scan all root bridge instances even when any
one root bridge meet bus resource OUT_OF_RESOURCE case.
thus platform handler of "EfiPciHostBridgeEndBusAllocation" has
an chance to do relative pci bus rebalance to handle this case.
Signed-off-by: Foster Nong <foster.nong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
|
|
REF: https://github.com/tianocore/edk2/pull/3130
The above PR removed UefiDevicePathLibStandaloneMm.inf, which is
a non-backwards compatible change and does not provide time for
downstream platforms to use the UefiDevicePathLibBase.inf.
Add UefiDevicePathLibStandaloneMm.inf back, but add comments that
it is deprecated and that UefiDevicePathLibBase.inf should be used
instead.
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Mateusz Albecki <mateusz.albecki@intel.com>
Cc: Yanbo Huang <yanbo.huang@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
|
|
The change doesn't change functionality behavior.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
|
|
With following paging structure to map
[2M-4K, 2M] as P = 1, RW = 0,
[2M, 4M] as P = 1, RW = 1:
PML4[0] -> PDPTE[0] -> PDE[0](RW = 0) -> PTE[255](P = 0, RW = 0)
-> PDE[1](RW = 1)
When a new request to map [2M-4K, 2M+4K] as P = 1, RW = 1,
CpuPageTableMap() wrongly requests 4K buffer size for the new mapping
request.
But in fact, for [2M-4K, 2M] request, PTE[255] can be changed in place,
for [2M, 2M+4K], no change is needed because PDE[1].RW = 1 already.
The change fixes the bug.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
|
|
With the following paging structure that maps [0, 2G] with ReadWrite
bit set.
PML4[0] --> PDPTE[0] --> PDE[0-255]
\-> PDPTE[1] --> PDE[0-255]
If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called
to change [0, 2M] as read-only, today's logic unnecessarily changes
the paging structure in 2 aspects:
1. When setting PageTableBaseAddress in the entry, the code clears
all attributes.
2. Even the ReadWrite bit in parent entry is not set, the code clears
the ReadWrite bit in the leaf entry.
First change is wrong. It should not change other attributes when
setting the PA.
Second change is unnecessary. Because the parent entry already
declares the whole region as read-only, there is no need to clear
ReadWrite bit in the leaf entry again.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
|
|
With the following paging structure that maps [0, 2G] with ReadWrite
bit set.
PML4[0] --> PDPTE[0] --> PDE[0-255]
\-> PDPTE[1] --> PDE[0-255]
If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called
to change [0, 2M] as writable, today's logic doesn't inherit the
parent entry's attributes when determining the child entry's
attributes. It just sets the PDPTE[0].PDE[0].ReadWrite bit.
But since the PML4[0].ReadWrite is 0, [0, 2M] is still read-only.
The change fixes the bug.
If the inheritable attributes in ParentPagingEntry conflicts with the
requested attributes, let the child entries take the parent attributes
and loosen the attribute in the parent entry.
E.g.: when PDPTE[0].ReadWrite = 0 but caller wants to map [0-2MB as
ReadWrite = 1 (PDE[0].ReadWrite = 1), we need to change
PDPTE[0].ReadWrite = 1 and let all PDE[0-255].ReadWrite = 0 first.
Then change PDE[0].ReadWrite = 1.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
|
|
Today's logic wrongly treats the non-leaf entry as leaf entry and
updates its paging attributes.
The patch fixes the bug to only update paging attributes for
non-present entries or leaf entries.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
|
|
When PageTableMap() is called to create non 1:1 mapping
such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the
4K page level, but old logic has a bug that it just uses 1G page
entry.
The patch fixes the bug.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
|
|
The patch replaces
LinearAddress + Offset == RegionStart
with
((LinearAddress + Offset) & RegionMask) == 0
The replace should not cause any behavior change.
Because:
1. In first loop of while when LinearAddress + Offset == RegionStart,
because the lower "BitStart" bits of RegionStart are all-zero,
all lower "BitStart" bits of (LinearAddress + Offset) are all-zero.
Because all lower "BitStart" bits of RegionMask is all-one and
bits are all-zero, ((LinearAddress + Offset) & RegionMask) == 0.
2. In following loops of the while, even RegionStart is increased
by RegionLength, the lower "BitStart" bits are still all-zero.
So the two expressions still semantically equal to each other.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
|
|
To reproduce the issue:
UINTN PageTable;
VOID *Buffer;
UINTN PageTableBufferSize;
IA32_MAP_ATTRIBUTE Attribute;
IA32_MAP_ATTRIBUTE Mask;
RETURN_STATUS Status;
Attribute.Uint64 = 0;
Mask.Uint64 = 0;
PageTableBufferSize = 0;
PageTable = 0;
Buffer = NULL;
Attribute.Bits.Present = 1;
Attribute.Bits.Nx = 1;
Mask.Bits.Present = 1;
Mask.Uint64 = MAX_UINT64;
//
// Create page table to cover [0, 10M)
//
Status = PageTableMap (
&PageTable, PagingMode, Buffer, &PageTableBufferSize,
0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask
);
ASSERT (Status == RETURN_BUFFER_TOO_SMALL);
Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize));
Status = PageTableMap (
&PageTable, PagingMode, Buffer, &PageTableBufferSize,
0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask
);
ASSERT (Status == RETURN_SUCCESS);
//
// Change the mapping for [0, 4KB)
// No change actually. Just clear Nx bit in Mask.
//
Mask.Bits.Nx = 0;
PageTableBufferSize = 0;
Status = PageTableMap (
&PageTable, PagingMode, NULL, &PageTableBufferSize,
0, (UINT64)SIZE_4KB, &Attribute, &Mask
);
ASSERT (Status == RETURN_SUCCESS); // FAIL!!
The root cause is when comparing the existing mapping attributes
against the requested one, Mask is not used but it should be used.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
|
|
When LinearAddress or Length is not aligned on 4KB, PageTableMap()
should return Invalid Parameter.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
|
|
The lib includes two APIs:
* PageTableMap
It creates/updates mapping from LA to PA.
The implementation only supports paging structures used in 64bit
mode now. PAE paging structure support will be added in future.
* PageTableParse
It parses the page table and returns the mapping relations in an
array of IA32_MAP_ENTRY.
It passed some stress tests. These test code will be upstreamed in
other patches following edk2 Unit Test framework.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
|
|
CPU_EXCEPTION_INIT_DATA is now an internal implementation of
CpuExceptionHandlerLib. Union can be removed since Ia32 and X64 have the
same definition. Also, two fields (Revision and InitDefaultHandlers)are
useless, can be removed.
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
|
|
Since the API InitializeSeparateExceptionStacks is simplified and does't
use the struct CPU_EXCEPTION_INIT_DATA, CPU_EXCEPTION_INIT_DATA become
a inner implementation of CpuExcetionHandlerLib.
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
|
|
Hide the Exception implementation details in CpuExcetionHandlerLib and
caller only need to provide buffer
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
|
|
Specify how to build the PrmPkg for the AArch64 architecture.
Make the 2 following notes:
- the PrmPkg has only been tested on AArch64 using the GCC5
toolchain.
- All symbols to be listed in the PRMT as well as the
PrmModuleExportDescriptor must be explicitly preserved by resorting to
the --require-defined linker flag.
Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
|
|
Add support to build PrmPkg for AArch64 using the GCC compiler.
Add AARCH64 architecture to the list of supported architectures.
Add BaseStackCheck library to allow for Prm module builds on AARCH64.
Also update the CI to add dependency on ArmPkg.
Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
|
|
- Add the --prm flag to the GENFW_FLAGS
- Add the --no-gc-section to the linker flags so that apparently
unreferenced symbols are not prematurely removed from the .dll which
is used to generate the Prm module .efi.
- Force the linker to maintain the PrmModuleExportDescriptor symbol.
- Force the linker to maintain the PRM handler funtion's symbol.
Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
|
|
Enable GCC compilations to keep external symbols when generating a PRM
module.
Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
|
|
The GenFw invocation with the --prm flag was previously reserved for
X64.
AArch64 platforms, built with GCC5, can also deploy PRM modules, hence
the --prm flag is also applicable in builds targeting the AARCH64
architecture.
This commit enables the --prm flag to be used for EDK2 builds targeting
AARCH64.
Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
|
|
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
|
