summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2024-05-27Add SM3 functions with openssl for MbedtlsWenxing Hou11-8/+1010
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177 Because the Mbedlts 3.3.0 doesn't have Sm3, the Sm3 implementaion is based on Openssl. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Yi Li <yi1.li@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Yi Li <yi1.li@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2024-05-27CryptoPkg: Update *.inf in BaseCryptLibMbedTlsWenxing Hou5-66/+80
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177 Update all *.inf in BaseCryptLibMbedTls based on new implementation. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Yi Li <yi1.li@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Yi Li <yi1.li@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2024-05-27CryptoPkg: Add ImageTimestampVerify based on MbedtlsWenxing Hou1-0/+381
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177 Timestamp Countersignature Verification implementaion based on Mbedtls. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Yi Li <yi1.li@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Yi Li <yi1.li@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2024-05-27CryptoPkg: Add AuthenticodeVerify based on MbedtlsWenxing Hou1-0/+214
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177 Implement AuthenticodeVerify based on Mbedtls. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Yi Li <yi1.li@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Yi Li <yi1.li@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2024-05-27CryptoPkg: Add more RSA related functions based on MbedtlsWenxing Hou3-0/+770
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177 Implement more RSA functions such as RsaPkcs1Sign based Mbedlts. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Yi Li <yi1.li@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Yi Li <yi1.li@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2024-05-27CryptoPkg: Add Pkcs5 functions based on MbedtlsWenxing Hou1-0/+100
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177 PBKDF2 Key Derivation Function Wrapper Implementation over MbedTLS. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Yi Li <yi1.li@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Yi Li <yi1.li@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2024-05-27CryptoPkg: Add Pkcs7 related functions based on MbedtlsWenxing Hou7-12/+2843
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177 Because the current Mbedlts pkcs7 library doesn't support authenticatedAttributes and only support 0 or 1 certificates in Signed data, the patch implement Pkcs7 by low Mbedtls Api. And the implementation has pass unit_tes and integration test. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Yi Li <yi1.li@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Yi Li <yi1.li@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2024-05-27CryptoPkg: Add X509 functions based on MbedtlsWenxing Hou1-0/+1940
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177 X.509 Certificate Handler Wrapper Implementation over MbedTLS. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Yi Li <yi1.li@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Yi Li <yi1.li@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2024-05-27CryptoPkg: Add Pem APIs based on MbedtlsWenxing Hou1-0/+138
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177 Implement Pem API based on Mbedtls. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Yi Li <yi1.li@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Yi Li <yi1.li@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2024-05-27CryptoPkg: Add rand function for BaseCryptLibMbedTlsWenxing Hou4-0/+246
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177 Add rand function for BaseCryptLibMbedTls. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Yi Li <yi1.li@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Yi Li <yi1.li@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2024-05-27CryptoPkg: Add AeadAesGcm based on MbedtlsWenxing Hou1-0/+227
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4177 AeadAesGcm implementation based on Mbedtls. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Yi Li <yi1.li@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Yi Li <yi1.li@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2024-05-27UefiCpuPkg/MpLib:Do not assume BSP is #0.Ning Feng1-18/+31
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4778 MPInitlib have wrong expectation that BSP index should always be 0 in MpInitLibInitialize(), SwitchBsp(),ApWakeupFunction(). That will cause the data mismatch, if the initial BSP is not 0. Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Ning Feng <ning.feng@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com>
2024-05-24ArmVirtPkg/ArmVirtQemu: Add RngDxe driveredk2-stable202405Ard Biesheuvel4-1/+7
Add the RngDxe driver to the build, backed by either RNDR or TRNG, one of which is expected to be available in most cases: - RNDR is implemented by the 'max' CPU that QEMU implements in TCG mode - TRNG is implemented by the KVM hypervisor, which backs QEMU's 'host' CPU Other TCG modes (e.g., the 'cortex-a*' CPUs) implement neither, which should prevent the RngDxe driver from dispatching entirely, resulting in the same situation as before. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2024-05-24ArmVirtPkg: Reverse inclusion order of MdeLibs.inc and ArmVirt.dsc.incArd Biesheuvel3-6/+6
MdeLibs.inc sets default library class resolutions which are much more general than the ones that might be specified in ArmVirt.dsc.inc. So the latter should be included *after* MdeLibs.inc to ensure that its definitions take precedence. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2024-05-24ArmVirtPkg: Use dynamic PCD to set the SMCCC conduitArd Biesheuvel6-0/+26
On ARM systems, whether SMC or HVC instructions need to be used to issue monitor calls is typically dependent on the exception level, but there are also cases where EL1 might use SMC instructions, so there is no hard and fast rule. For ArmVirtQemu, this does depend strictly on the exception level, so set the default to HVC (for EL1 execution) and override it to SMC when booted at EL2. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2024-05-24ArmVirtPkg/ArmVirtQemu: Permit the use of dynamic PCDs in PEIArd Biesheuvel2-6/+2
Currently, only TPM2 builds enable the PCD PEIM, which is a prerequisite for being able to use dynamic PCDs already at the PEI stage. This facility will be used for other reasons too so move those pieces out of code block that are conditional on TPM2_ENABLE Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2024-05-24MdePkg/BaseRngLib AARCH64: Remove overzealous ASSERT()Ard Biesheuvel1-1/+0
BaseRngLib on AARCH64 will discover whether or not RNDR instructions are supported, by inspecting the ISAR0 identification register, and setting a global boolean accordingly. This boolean is used in subsequent execution to decide whether or not to issue the instruction. The same discovery code also ASSERT()s that RNDR instructions are implemented, which is unnecessary, and breaks execution on systems that incorporate the library but don't implement the instruction (or fail to expose it to the exception level that the firmware executes at). So drop the ASSERT(). Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-24ArmVirtPkg: Move PcdMonitorConduitHvcFlickdm1-2/+2
This moves the PcdMonitorConduitHvc from PcdsFeatureFlag.Common to PcdsFixedAtBuild.Common This is a follow on to the previous commit: ArmPkg: Allow SMC/HVC monitor conduit to be specified at runtime ArmVirtQemu may execute at EL2, in which case monitor calls are generally made using SMC instructions instead of HVC instructions. Whether or not this is the case can only be decided at runtime, and so the associated PCD needs to be settable at runtime, if the platform definition chooses so. This implies a boolean PCD, given that a feature PCD is build-time configurable only. Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2024-05-24ArmPkg: Allow SMC/HVC monitor conduit to be specified at runtimeArd Biesheuvel2-6/+6
ArmVirtQemu may execute at EL2, in which case monitor calls are generally made using SMC instructions instead of HVC instructions. Whether or not this is the case can only be decided at runtime, and so the associated PCD needs to be settable at runtime, if the platform definition chooses so. This implies a boolean PCD, given that a feature PCD is build-time configurable only. Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2024-05-24NetworkPkg: Update the PxeBcDhcp6GoogleTest due to underlying changesDoug Flick3-6/+100
This patch updates the PxeBcDhcp6GoogleTest due to the changes in the underlying code. The changes are as follows: - Random now comes from the RngLib Protocol - The TCP ISN is now generated by the hash function Cc: Saloni Kasbekar <saloni.kasbekar@intel.com> Cc: Zachary Clark-williams <zachary.clark-williams@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
2024-05-24MdePkg: Add MockHash2 Protocol for testingDoug Flick2-0/+94
This commit adds a new MockHash2 protocol to the MdePkg. This allows the unit tests to pick up the new protocol and use it for testing. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-24MdePkg: Adds Protocol for MockRngDoug Flick2-0/+69
This patch adds a protocol for MockRng. This protocol is used to mock the Rng protocol for testing purposes. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-24MdePkg: Add MockUefiBootServicesTableLibDoug Flick4-0/+180
This commit adds a mock library for UefiBootServicesTableLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-24NetworkPkg TcpDxe: SECURITY PATCH CVE-2023-45236Doug Flick8-49/+415
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4541 REF: https://www.rfc-editor.org/rfc/rfc1948.txt REF: https://www.rfc-editor.org/rfc/rfc6528.txt REF: https://www.rfc-editor.org/rfc/rfc9293.txt Bug Overview: PixieFail Bug #8 CVE-2023-45236 CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N CWE-200 Exposure of Sensitive Information to an Unauthorized Actor Updates TCP ISN generation to use a cryptographic hash of the connection's identifying parameters and a secret key. This prevents an attacker from guessing the ISN used for some other connection. This is follows the guidance in RFC 1948, RFC 6528, and RFC 9293. RFC: 9293 Section 3.4.1. Initial Sequence Number Selection A TCP implementation MUST use the above type of "clock" for clock- driven selection of initial sequence numbers (MUST-8), and SHOULD generate its initial sequence numbers with the expression: ISN = M + F(localip, localport, remoteip, remoteport, secretkey) where M is the 4 microsecond timer, and F() is a pseudorandom function (PRF) of the connection's identifying parameters ("localip, localport, remoteip, remoteport") and a secret key ("secretkey") (SHLD-1). F() MUST NOT be computable from the outside (MUST-9), or an attacker could still guess at sequence numbers from the ISN used for some other connection. The PRF could be implemented as a cryptographic hash of the concatenation of the TCP connection parameters and some secret data. For discussion of the selection of a specific hash algorithm and management of the secret key data, please see Section 3 of [42]. For each connection there is a send sequence number and a receive sequence number. The initial send sequence number (ISS) is chosen by the data sending TCP peer, and the initial receive sequence number (IRS) is learned during the connection-establishing procedure. For a connection to be established or initialized, the two TCP peers must synchronize on each other's initial sequence numbers. This is done in an exchange of connection-establishing segments carrying a control bit called "SYN" (for synchronize) and the initial sequence numbers. As a shorthand, segments carrying the SYN bit are also called "SYNs". Hence, the solution requires a suitable mechanism for picking an initial sequence number and a slightly involved handshake to exchange the ISNs. Cc: Saloni Kasbekar <saloni.kasbekar@intel.com> Cc: Zachary Clark-williams <zachary.clark-williams@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
2024-05-24NetworkPkg: SECURITY PATCH CVE-2023-45237Doug Flick27-83/+410
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4542 Bug Overview: PixieFail Bug #9 CVE-2023-45237 CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:L/I:N/A:N CWE-338 Use of Cryptographically Weak Pseudo-Random Number Generator (PRNG) Use of a Weak PseudoRandom Number Generator Change Overview: Updates all Instances of NET_RANDOM (NetRandomInitSeed ()) to either > > EFI_STATUS > EFIAPI > PseudoRandomU32 ( > OUT UINT32 *Output > ); > or (depending on the use case) > > EFI_STATUS > EFIAPI > PseudoRandom ( > OUT VOID *Output, > IN UINTN OutputLength > ); > This is because the use of Example: The following code snippet PseudoRandomU32 () function is used: > > UINT32 Random; > > Status = PseudoRandomU32 (&Random); > if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "%a failed to generate random number: %r\n", __func__, Status)); > return Status; > } > This also introduces a new PCD to enable/disable the use of the secure implementation of algorithms for PseudoRandom () and instead depend on the default implementation. This may be required for some platforms where the UEFI Spec defined algorithms are not available. > > PcdEnforceSecureRngAlgorithms > If the platform does not have any one of the UEFI defined secure RNG algorithms then the driver will assert. Cc: Saloni Kasbekar <saloni.kasbekar@intel.com> Cc: Zachary Clark-williams <zachary.clark-williams@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
2024-05-24SecurityPkg RngDxe: Remove incorrect limitation on GetRngFlickdm1-8/+0
Removed from gEfiRngAlgorithmRaw an incorrect assumption that Raw cannot return less than 256 bits. The DRNG Algorithms should always use a 256 bit seed as per nist standards however a caller is free to request less than 256 bits. > > // > // When a DRBG is used on the output of a entropy source, > // its security level must be at least 256 bits according to UEFI Spec. > // > if (RNGValueLength < 32) { > return EFI_INVALID_PARAMETER; > } > AARCH64 platforms do not have this limitation and this brings both implementations into alignment with each other and the spec. Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Jiewe Yao <Jiewen.yao@intel.com>
2024-05-24ArmVirtPkg: Add Hash2DxeCrypto to ArmVirtPkgFlickdm3-0/+15
This patch adds Hash2DxeCrypto to ArmVirtPkg. The Hash2DxeCrypto is used to provide the hashing protocol services. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2024-05-24ArmVirtPkg PlatformCI: Support virtio-rng-pciFlickdm1-0/+2
This patch adds "virtio-rng-pci" to the PlatformBuildLib.py This adds Rng services to the guest VM Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2024-05-24OvmfPkg: Add Hash2DxeCrypto to OvmfPkgDoug Flick8-3/+40
This patch adds Hash2DxeCrypto to OvmfPkg. The Hash2DxeCrypto is used to provide the hashing protocol services. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2024-05-24OvmfPkg PlatformCI: Support virtio-rng-pciFlickdm1-0/+2
This patch adds "virtio-rng-pci" to the PlatformBuildLib.py This adds Rng services to the guest VM Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2024-05-24EmulatorPkg: Add Hash2DxeCrypto to EmulatorPkgDoug Flick2-2/+12
This patch adds Hash2DxeCrypto to EmulatorPkg. The Hash2DxeCrypto is used to provide the hashing protocol services. Cc: Andrew Fish <afish@apple.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ray Ni <ray.ni@Intel.com>
2024-05-24EmulatorPkg: Add RngDxe to EmulatorPkgFlickdm2-2/+11
This patch adds RngDxe to EmulatorPkg. The RngDxe is used to provide random number generation services to the UEFI firmware. Cc: Andrew Fish <afish@apple.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2024-05-21CodeQL: Update from 2.16.1 to 2.17.3Michael Kubacki3-9/+9
This fixes an issue where the CodeQL queries currently fetched in the pipeline are incompatible with the current executable used. Update to pick up functional and security fixes. See the following comparison for detailed differences: https://github.com/github/codeql-cli-binaries/compare/v2.16.1...v2.17.3 Cc: Bob Feng <bob.c.feng@intel.com> Cc: Joey Vagedes <joey.vagedes@gmail.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Yuwei Chen <yuwei.chen@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2024-05-17MdeModulePkg: Potential UINT32 overflow in S3 ResumeCountShanmugavel Pakkirisamy1-4/+8
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4677 Attacker able to modify physical memory and ResumeCount. System will crash/DoS when ResumeCount reaches its MAX_UINT32. Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Pakkirisamy ShanmugavelX <shanmugavelx.pakkirisamy@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-15MdePkg/BaseLib: Fix AARCH64 compilation errorShun Cheng Liu2-0/+2
Declare InternalAssertJumpBuffer as EXTERN Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Shun Cheng Liu <adam.liu@tw.synaptics.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com>
2024-05-10MdePkg: Add MmUnblockMemoryLib to MdeLibs.dscRay Ni1-1/+2
MdeLibs.dsc.inc included some default libraries provided by MdePkg. Platform can include MdeLibs.dsc.inc file to avoid some potential incompatible changes to platform dsc file in future. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com> Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
2024-05-10DynamicTablesPkg: Adds integer to the AML package nodeAbdul Lateef Attar2-1/+107
Adds an AmlAddIntegerToNamedPackage() API to generate AML code, which adds an integer value to the package node. Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2024-05-09MdePkg: Updated SpcrTable structure for Revision_4praveensankarn1-0/+32
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4656 In SPCR table, 4 structure members have been added newly as per SPCR table Revision 4, which has to be added in MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h. Signed-off-by: Praveen Sankar N <praveensankarn@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Felix Polyudov <Felixp@ami.com> Cc: Srinivasan Mani <srinivasanm@ami.com> Cc: Sundaresan S <sundaresans@ami.com> Cc: Rabisha R <rabishar@ami.com>
2024-05-08OvmfPkg: Use newly defined Unaccepted Memory TypeSachin Ganesh5-14/+14
EFI_RESOURCE_MEMORY_UNACCEPTED has been officially defined in the PI 1.8 specification. So all temporary solutions have been replaced with the actual definition. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
2024-05-08MdePkg: Update Delayed Dispatch PPI as per PI 1.8 SpecSachin Ganesh1-1/+23
Added WaitOnEvent() function to EFI_DELAYTED_DISPATCH_PPI. Modified DispatchRegister() parameter list. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-08MdeModulePkg: Use newly defined Unaccepted Memory TypeSachin Ganesh4-69/+24
EFI_RESOURCE_MEMORY_UNACCEPTED has been officially defined in the PI 1.8 specification. So all temporary solutions have been replaced with the actual definition. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-08MdePkg: Define Unaccepted Memory TypeSachin Ganesh2-18/+7
EFI_RESOURCE_MEMORY_UNACCEPTED has been officially defined in the PI 1.8 specification. So all temporary solutions have been replaced with the actual definition. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-08MdePkg: Add new Resource Attributes defined in PI 1.8 SpecSachin Ganesh1-0/+2
Defined Encrypted and Special Purpose resource attributes as defined in PI 1.8 Specification Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-08MdePkg: Add definition for NVMe Over Fabric Device PathSachin Ganesh1-0/+22
In accordance with UEFI 2.10 Specification: Adding definition for NVMe Over Fabric (NVMe-oF) Device Path of Messaging Sub-Type. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-08UefiCpuPkg/Library: Support to get processor extended infoJiaxin Wu2-4/+4
Intel has some features need to use processor extended information under CPU feature InitializeFunc(), so add code to support it: This patch is to add CPU_V2_EXTENDED_TOPOLOGY to get processor extended info. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2024-05-08MdeModulePkg: Adding SpiHc DriversBrit Chesley1-0/+2
Including the SpiHc drivers in MdeModulePkg.dsc Bugzilla #4753 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-08MdeModulePkg: SpiHc: SpiHc DriversBrit Chesley7-0/+514
Added SpiHc DXE and SMM drivers. This code receives bus transactions from the SpiBus layer and passes them onto the SpiHcPlatformLib Platform Initialization Spec 1.7 volume 5 section 18.1.7 Bugzilla #4753 Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
2024-05-08MdeModulePkg:BaseSpiHcPlatformLib: Adding NULL lib instanceBrit Chesley6-0/+344
Adding NULL SpiHcPlatformLib instance. This library is responsible for handling the low level details of the SPI host controller. Since this is platform specific this library will be dependent on OEM SPI implementation. The SPI host controller layer will utilize this library for SPI bus transactions. Bugzilla #4753 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-08MdeModulePkg: Adding SpiBus DriversBrit Chesley1-0/+2
Including the SpiBus drivers in MdeModulePkg.dsc Platform Initialization spec 1.7 volume 5 section 18.1.6 Bugzilla #4753 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-05-08MdeModulePkg/Bus/Spi/SpiBus: Adding SpiBus DriversBrit Chesley7-0/+1052
Added SpiBus DXE and SMM drivers. This code translates SPI requests from the application layer into SPI Bus transactions on the SPI host controller. The code is responsible for checking if the transaction is valid, then setting up the SPI clock and chip select properly before passing the bus transaction to the host controller. Platform Initialization Spec 1.7 volume 5 section 18.1.6 Bugzilla #4753 Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
generated by cgit v1.1 at 2024-10-18 19:05:48 +0000