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2018-02-07SecurityPkg:Tcg2Smm: Fix compile issueZhang, Chao B1-3/+4
Update Tcg2Smm _PRS patching logic to fix compile issue Cc: Liming Gao <liming.gao@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-02-07MdePkg ACPI: Add some macros for PPTTHeyi Guo1-0/+18
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang <huangming23@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-02-06ArmPkg/Gic: force GIC driver to run before CPU arch protocol driverArd Biesheuvel5-25/+54
Currently, the GIC driver has a static dependency on the CPU arch protocol driver, so it can register its IRQ handler at init time. This means there is a window between dispatch of the CPU driver and dispatch of the GIC driver where any unexpected GIC state may trigger an interrupt which we are not set up to handle yet. Note that this is even the case if we enter UEFI with interrupts disabled at the CPU, given that any TPL manipulation involving TPL_HIGH_LEVEL will unconditionally enable IRQs at the CPU side regardless of whether they were enabled to begin with (but only as soon as the CPU arch protocol is actually installed) So let's reorder the GIC driver with the CPU driver, and let it run its initialization that puts the GIC into a known state before enabling interrupts. Move its installation of its IRQ handler to a protocol notify callback on the CPU arch protocol so that it runs as soon as it becomes available. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Marc Zyngier <marc.zyngier@arm.com>
2018-02-06EmbeddedPkg: delete unused Pcds and guidsLeif Lindholm2-59/+0
Delete a bunch of Pcds, a guid, and a related header file - probably Ebl related. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-02-06EmbeddedPkg: delete unused HalRuntimeServicesExampleLibLeif Lindholm6-1943/+0
HalRuntimeServicesExampleLib contains no .inf and none of its contents are included elsewhere - so get rid of it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-02-06EmbeddedPkg: drop unused Pcds from package .dscLeif Lindholm1-15/+0
A bunch of Ebl-related Pcds are still referenced in package Pcd. Drop them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-02-06ArmPkg: delete references to unused guids/Pcds from CpuDxeLeif Lindholm2-3/+0
gEfiDebugSupportPeriodicCallbackProtocolGuid and PcdCpuDxeProduceDebugSupport are referred to from CpuDxe. Delete references from .inf and .h. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-02-06BeagleBoardPkg: drop unused EmbeddedPkg PcdsLeif Lindholm2-23/+1
Drop a bunch of unused EmbeddedPkg Pcds, including one used in local code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-02-06ArmVirtPkg: drop unused PcdCacheEnableLeif Lindholm1-2/+0
ArmVirt.dsc.inc sets gEmbeddedTokenSpaceGuid.PcdCacheEnable, which is unused and about to be deleted. Drop it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-02-06BaseTools/Conf: disable DTC legacy phandle formatArd Biesheuvel2-1/+2
By default, the device tree compiler emits phandle properties twice: once called 'phandle' and again called 'linux,phandle'. Given that Linux was updated in early 2010 [0] to accept the former (which is what is specified in the ePAPR and device tree specifications), there is no point in emitting both when compiling device trees for UEFI platforms. [0] 04b954a673dd02f585a2769c4945a43880faa989 "of/flattree: Make the kernel accept ePAPR style phandle information" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-02-06ShellPkg/map: Fix out-of-bound read when "map fsn"Ruiyu Ni1-6/+12
The below code reads additional one CHAR16 when copying content from Specific to NewSpecific. NewSpecific = AllocateCopyPool( StrSize(Specific) + sizeof(CHAR16), Specific ); The patch fixes this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com>
2018-02-06MdePkg/SafeString: Fix potential out-of-bound memory accessRuiyu Ni1-9/+9
Today's implementation of [Ascii]StrnCpyS/[Ascii]StrnCatS calls StrnLenS () to get the length of source string but supplies the destination buffer size as max size. It's a bug that may cause out-of-bound memory access. For example: StrnCpyS (Dest[10], 10, "hello", 6) -> StrnLenS ("hello", 10) //< cause out-of bound memory access In a pool guard enabled environment, when using shell to edit an existing file which contains empty line, the page fault is met. The patch fixes the four library functions to avoid such out-of-bound memory access. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com>
2018-02-06ShellPkg/for: Fix potential null pointer deferenceRuiyu Ni1-2/+4
When "FOR %a %a IN A B C" is executed, CurrentScriptFile->CurrentCommand->Data is NULL. But the code assumes it's not NULL and tries to deference it. The patch fixes this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
2018-02-06BaseTools: enhance error check for DatumType formatYonghong Zhu1-1/+6
Add a check for DatumType format, eg: VOID *, original Tool will crash but no detail error message which cause confusion to user. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-02-06BaseTools GNUmakefile: Remove HOST_ARCH in every tool MakefileLiming Gao18-36/+18
HOST_ARCH has been moved into the common header.makefile Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
2018-02-06BaseTools GNUmakefile: Move HOST_ARCH detection into common makefileLiming Gao1-2/+26
With this change, enter single tool directory, make can pass. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2018-02-06PcAtChipsetPkg: Add PeiAcpiTimerLib to save Frequency in HOBLiming Gao7-8/+212
In V2: 1) Update PeiAcpiTimerLib base name to PeiAcpiTimerLib 2) Update PeiAcpiTimerLib to add the missing constructor to enable ACPI IO space 3) Update DxeAcpiTimerLib to cache frequency in constructor. PeiAcpiTimerLib caches PerformanceCounterFrequency in HOB, then Pei and Dxe AcpiTimerLib can share the same PerformanceCounterFrequency. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-02-06SecurityPkg: Support PP version lower than 1.3Zhang, Chao B2-8/+30
TCG PP 1.2 & PP 1.3 spec defined different Opcodes. Update code to support both. Cc: Long Qin <qin.long@intel.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Long Qin <qin.long@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
2018-02-05CorebootPayloadPkg/FbGop: Produces correct PixelsPerScanLineBenjamin You1-1/+1
According to UEFI Spec, EFI_GRAPHICS_OUTPUT_PROTOCOL.Mode->Info-> PixelsPerScanLine may contain padding pixel elements outside the area covered by HorizontalResolution for performance reasons or due to hardware restrictions. CorebootPayloadPkg's FbGop driver doesn't follow this requirement, and produces PixelsPerScanLine simply as HorizontalResolution. This needs to be fixed to reflect the real length of a framebuffer scanline. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2018-02-05MdeModulePkg/PXE: Add warning message for PXE if failed to read system GUID ↵Fu Siyuan1-1/+4
from SMBIOS. Current PXE driver uses zero GUID if failed to get the system GUID from smbios table, and some OS PXE boot may fail in such case. This patch is to add a warning message to inform user that smbios table is missed on the platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
2018-02-05NetworkPkg: Add warning message for PXE if failed to read system GUID from ↵Fu Siyuan2-0/+4
SMBIOS. Current PXE driver uses zero GUID if failed to get the system GUID from smbios table, and some OS PXE boot may fail in such case. This patch is to add a warning message to inform user that smbios table is missed on the platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
2018-02-05SecurityPkg: Add UNI string for 2 PCDsZhang, Chao B1-1/+10
Add prompt & help string for PcdTpm2CurrentIrqNum, PcdTpm2PossibleIrqNumBuf Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
2018-02-04BaseTools: Update Expression.py for VOID* to support L'a' and 'a'Feng, YunhuaX2-3/+20
Original VOID* type support L"string" and "string" format, now we also add support for single quote string that without null terminator. Type VOID* support L'a' and 'a', the value transfer to c style value. L'a' --> {0x61, 0x00} L'ab' --> {0x61, 0x00, 0x62, 0x00} 'a' --> {0x61} 'ab' --> {0x61, 0x62} when the value is L'' or '' that not include any character, tool will report error. Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yunhua Feng <yunhuax.feng@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2018-02-04BaseTools: StructurePcd array Value support flexible formatFeng, YunhuaX1-2/+33
if StructurePcd set item value is array, support flexible format like as: gEfiStructuredPcdPkgTokenSpaceGuid.Test.Array | {flexible format} {flexible format} = {L"ABC"} | {L'ABC'} | {"ABC"} | {UINT8(0x10)} | {UINT16(0x10)} | {UINT32(0x10)} | {UINT64(0x10)} | {DEVICE_PATH("PciRoot(0)/Pci(0,0)")} | {GUID(gPcdPkgTokenSpaceGuid)} | {L"ABC", L'ABC', UINT8(0x10)....} Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yunhua Feng <yunhuax.feng@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2018-02-03MdeModulePkg/SmmCore: Fix hang due to already-freed memory deferenceRuiyu Ni1-5/+32
SmiHandlerUnRegister() validates the DispatchHandle by checking whether the first 32bit matches to a certain signature (SMI_HANDLER_SIGNATURE). But if a caller calls *UnRegister() twice and the memory freed by first call still contains the signature, the second call may hang. The patch fixes this issue by locating the DispatchHandle in all SMI handlers, instead of checking the signature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-02-02IntelSiliconPkg/MicrocodeUpdateDxe: Refine debug messagesHao Wu1-5/+14
Refine the debug messages during the verification of microcode to make them more clear. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-02-02BaseTools: Fix make PcdValueCommon.c failure on GCCFeng, YunhuaX1-2/+1
error message: PcdValueCommon.c: In function '__PcdGetPtr': PcdValueCommon.c:315:11: error: variable 'Byte' set but not used [-Werror=unused-but-set-variable] UINT8 Byte; ^ cc1: all warnings being treated as errors Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yunhua Feng <yunhuax.feng@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2018-02-02MdeModulePkg/Core: fix feature conflict between NX and heap guardJian J Wang3-0/+46
Considering following scenario (both NX memory protection and heap guard are enabled): 1. Allocate 3 pages. The attributes of adjacent memory pages will be |NOT-PRESENT| present | present | present |NOT-PRESENT| 2. Free the middle page. The attributes of adjacent memory pages should be |NOT-PRESENT| present |NOT-PRESENT| present |NOT-PRESENT| But the NX feature will overwrite the attributes of middle page. So it looks still like below, which is wrong. |NOT-PRESENT| present | PRESENT | present |NOT-PRESENT| The solution is checking the first and/or last page of a memory block to be marked as NX, and skipping them if they are Guard pages. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2018-02-02MdeModulePkg/Core: fix feature conflict between NX and NULL detectionJian J Wang1-4/+18
If enabled, NX memory protection feature will mark all free memory as NX (non-executable), including page 0. This will overwrite the attributes of page 0 if NULL pointer detection feature is also enabled and then compromise the functionality of it. The solution is skipping the NX attributes setting to page 0 if NULL pointer detection feature is enabled. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2018-02-02MdeModulePkg/Core: fix guard page missing issueJian J Wang2-12/+11
This issue is a regression one caused by a patch at 425d25699be83c35e12df8470b827d7fbcef3bce That fix didn't take the 0 page to free into account, which still needs to call UnsetGuardPage() even no memory needs to free. The fix is just moving the calling of UnsetGuardPage() to the place right after calling AdjustMemoryF(). Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2018-02-01IntelFrameworkModule/ThunkKb: ReadKeyStrokeEx always return key stateRuiyu Ni2-4/+15
Today's implementation only return key state when there is a key. But when user doesn't press any key, the key state cannot be returned. The patch changes the ReadKeyStrokeEx() to always return the key state even there is no key pressed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
2018-02-01IntelFrameworkModule/Ps2Kb: ReadKeyStrokeEx always return key stateRuiyu Ni3-24/+54
Today's implementation only return key state when there is a key. But when user doesn't press any key, the key state cannot be returned. The patch changes the ReadKeyStrokeEx() to always return the key state even there is no key pressed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
2018-02-01MdeModulePkg/Ps2Kb: ReadKeyStrokeEx always return key stateRuiyu Ni3-24/+54
Today's implementation only return key state when there is key. But when user doesn't press any key, the key state cannot be returned. The patch changes the ReadKeyStrokeEx() to always return the key state even there is no key pressed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
2018-02-01MdeModulePkg/UsbKb: ReadKeyStrokeEx always return key stateRuiyu Ni3-48/+77
Today's implementation only return key state when there is key. But when user doesn't press any key, the key state cannot be returned. The patch changes the ReadKeyStrokeEx() to always return the key state even there is no key pressed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
2018-02-01MdeModulePkg/ConSplitter: ReadKeyStrokeEx always return key stateRuiyu Ni2-25/+151
Today's implementation only return key state when there is key. But when user doesn't press any key, the key state cannot be returned. The patch changes the ReadKeyStrokeEx() to always return the key state even there is no key pressed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
2018-02-01MdePkg/SimpleTextInEx.h: Fix comments alignmentRuiyu Ni1-8/+5
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-02-01BaseTools CommonLib: Remove the unnecessary print message in PcdValueCommonLiming Gao1-10/+0
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2018-02-01UefiCpuPkg: Remove the unused file ResetVec.asm16Liming Gao1-106/+0
ResetVec.nasmb is used. ResetVec.asm16 can be retired. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2018-02-01MdePkg SafeIntLib: Update API definition to use the same output nameLiming Gao1-6/+6
In SafeUintnToChar8(), update its output parameter name. Update pui8Result --> Result to match its library implementation Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2018-02-01BaseTools: Structure Pcd in CommandLine.Feng, Bob C7-98/+233
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-02-01BaseTools: Support multiple .h fileFeng, Bob C4-7/+9
for structure Pcd declaration in DEC file. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-02-01BaseTool: Enhance error handling.BobCF1-49/+67
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-02-01BaseTool: Add comments in PcdValueInit.c.Feng, Bob C1-4/+6
Add Comments for __FLEXIBLE_SIZE () statement. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-01-31UefiCpuPkg/PiSmmCpuDxeSmm: eliminate conditional jump in IA32 SmmStartup()Laszlo Ersek1-4/+3
SMM emulation under both KVM and QEMU (TCG) crashes the guest when the "jz" branch, added in commit d4d87596c11d ("UefiCpuPkg/PiSmmCpuDxeSmm: Enable NXE if it's supported", 2018-01-18), is taken. Rework the propagation of CPUID.80000001H:EDX.NX [bit 20] to IA32_EFER.NXE [bit 11] so that no code is executed conditionally. Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Ref: http://mid.mail-archive.com/d6fff558-6c4f-9ca6-74a7-e7cd9d007276@redhat.com Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> [lersek@redhat.com: XD -> NX code comment updates from Ray] Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> [lersek@redhat.com: mark QEMU/TCG as well in the commit message]
2018-01-31UefiCpuPkg/PiSmmCpuDxeSmm: remove unneeded DBs from IA32 SmmStartup()Laszlo Ersek1-7/+6
The SmmStartup() executes in SMM, which is very similar to real mode. Add "BITS 16" before it and "BITS 32" after it (just before the @32bit label). Remove the manual 0x66 operand-size override prefixes, for selecting 32-bit operands -- the sizes of our operands trigger NASM to insert the prefixes automatically in almost every spot. The one place where we have to add it back manually is the LGDT instruction. (The 0x67 address-size override prefix is also auto-generated.) This patch causes NASM to generate byte-identical object code (determined by disassembling both the pre-patch and post-patch versions, and comparing the listings), except: > @@ -158,7 +158,7 @@ > 00000142 6689D3 mov ebx,edx > 00000145 66B800000000 mov eax,0x0 > 0000014B 0F22D8 mov cr3,eax > -0000014E 67662E0F0155F6 o32 lgdt [cs:ebp-0xa] > +0000014E 2E66670F0155F6 o32 lgdt [cs:ebp-0xa] > 00000155 66B800000000 mov eax,0x0 > 0000015B 0F22E0 mov cr4,eax > 0000015E 66B9800000C0 mov ecx,0xc0000080 The only difference is the prefix list order, it changes from: - 0x67, 0x66, 0x2E to - 0x2E, 0x66, 0x67 (0x2E is "CS segment override"). Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2018-01-31UefiCpuPkg/PiSmmCpuDxeSmm: update comments in IA32 SmmStartup()Laszlo Ersek1-4/+4
The gSmmCr3, gSmmCr4, gSmmCr0 and gSmmJmpAddr global variables are used for patching assembly instructions, thus we can't yet remove the DB encodings for those instructions. At least we should add the intended meanings in comments. This patch only changes comments. Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> [lersek@redhat.com: adapt commit msg to ongoing PatchAssembly discussion]
2018-01-31BaseTools: Update BPDG to support L'' and '' format as VPD Pcd ValueYonghong Zhu2-17/+21
Current Pcd value support flexible format, this patch add support for BPDG Tool to support L'' and '' format. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-01-31BaseTools: Fix the bug to align VPD PCD based on value typeYonghong Zhu1-2/+12
Spec required for VOID* VPD Pcd, Ascii string use byte alignment, byte array use 8-byte alignment, unicode string use 2-byte alignment. while when the VPD pcd offset use *, the offset generated in the .map file not follow this rule. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-01-31MdeModulePkg PiSmmCore: Set ForwardLink to NULL in RemoveOldEntry()Star Zeng1-1/+3
"Entry->Link.ForwardLink = NULL;" is present in RemoveMemoryMapEntry() for DxeCore, that is correct. "Entry->Link.ForwardLink = NULL;" is absent in RemoveOldEntry() for PiSmmCore, that is incorrect. Without this fix, when FromStack in Entry is TRUE, the "InsertTailList (&mMapStack[mMapDepth].Link, &Entry->Link);" in following calling to CoreFreeMemoryMapStack() will fail as the entry at mMapStack[mMapDepth] actually has been removed from the list. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-31MdePkg ACPI: Correct processor struct of PPTTMing Huang1-1/+1
The Type field of EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR should be UINT8 as ACPI version 6.2 specification. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang <huangming23@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
generated by cgit v1.1 at 2024-10-10 11:16:00 +0000