summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2016-03-22ArmPkg/ArmExceptionLib: fold exception handler prologue into vector tableArd Biesheuvel1-73/+39
Unlike the AArch32 vector table, which has room for a single instruction for each exception type, the AArch64 exception table has 128 byte slots, which can easily hold the shared prologues that are emitted out of line. So refactor this code into a single macro, and expand it into each vector table slot. Since the address of the command handler entry point is no longer patched in by the C code, we can just emit the literal into each vector entry directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
2016-03-22ArmPkg/AsmMacroIoLibV8: remove undocumented assumption from ELx macrosArd Biesheuvel1-8/+8
The macros EL1_OR_EL2() and EL1_OR_EL2_OR_EL3() allow conditional execution of assembly sequences based on the current exception level, by jumping to caller supplied labels 1f, 2f or 3f. However, the jump to 1f is actually a fallthrough, which means the EL1 code needs to follow right after the macro invocation, and the 1f label is ignored. So let's fix this by making all jumps explicit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
2016-03-22BaseTools: Fix nmake failure due to command-line length limitationYonghong Zhu4-2/+135
NMAKE is limited to command-line length of 4096 characters. Due to the large number of /I directives specified on command line (one per include directory), the path length of WORKSPACE is multiplied by the number of /I directives and can exceed the limit. This patch: 1. Add new build option -l, --cmd-len to set the maximum command line length, default value is 4096. 2. Generate the response file only if the command line length exceed its maximum characters (default is 4096) when build the module. Cover PP_FLAGS, CC_FLAGS, VFRPP_FLAGS, APP_FLAGS, ASLPP_FLAGS, ASLCC_FLAGS and ASM_FLAGS. 3. The content of the response file is combine from the FLAGS option and INC option. 4. When build failure, it would print out the response file's file location and its content. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-22MdePkg/Pci22.h: Fix a coding style issueRuiyu Ni1-6/+5
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Shumin Qiu <shumin.qiu@intel.com>
2016-03-22MdeModulePkg DxeCore: Address boundary check for Type AllocateAddressStar Zeng1-0/+26
Check for Type AllocateAddress, if NumberOfPages is 0 or if (NumberOfPages << EFI_PAGE_SHIFT) is above MAX_ADDRESS or if (Start + NumberOfBytes) rolls over 0 or if Start is above MAX_ADDRESS or if End is above MAX_ADDRESS, return EFI_NOT_FOUND. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-22MdeModulePkg DxeCore: Check Start consistently in CoreConvertPagesExStar Zeng1-2/+2
Current check: ASSERT (NumberOfPages); ASSERT ((Start & EFI_PAGE_MASK) == 0); ASSERT (End > Start) ; if (NumberOfPages == 0 || ((Start & EFI_PAGE_MASK) != 0) || (Start > (Start + NumberOfBytes))) { This patch is to update "(Start > (Start + NumberOfBytes))" to "(Start >= End)" to be consistent with "ASSERT (End > Start)" Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-21Nt32Pkg: Switch the DebugLibReportStatusCode to MdeModulePkgCinnamon Shia1-1/+1
Switch the DebugLibReportStatusCode from IntelFrameworkPkg to MdeModulePkg. The functionality and the code between them are almost the same. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Cinnamon Shia <cinnamon.shia@hpe.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-19OvmfPkg/PlatformPei: suppress wrong VS2008 warning (use of uninited local)Laszlo Ersek1-0/+1
VS2008 seems to think that the "PciExBarBase" variable (introduced in commit 7b8fe63561b4) can be evaluated for the AddReservedMemoryBaseSizeHob() function call with its value being uninitialized / indeterminate. This is not the case (see "mHostBridgeDevId"); suppress the warning. Reported-by: David Woodhouse <dwmw2@infradead.org> Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/8871/focus=9431 Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: David Woodhouse <David.Woodhouse@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-18MdeModulePkg PlatformVarCleanupLib: Locate VarCheck protocol when usingStar Zeng2-11/+11
Do not locate VarCheck protocol in Constructor, then the gEdkiiVarCheckProtocolGuid could be removed from [Depex]. It will be more flexible for the library Consumer to work without VarCheck protocol installed, for example at recovery boot mode with EmuRuntimeDxe. The unused UefiLib is also been removed from [LibraryClasses] in *.inf. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-03-17ArmPkg: update CpuDxe to use CpuExceptionHandlerLibCohen, Eugene7-1402/+98
Use the new ARM/AArch64 implementation of the base CpuExceptionHandlerLib library from CpuDxe to centralize exception handling. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-03-17Omap35xxPkg: drop CpuExceptionHandlerLib library class resolutionArd Biesheuvel1-1/+0
Remove the null resolution for CpuExceptionHandlerLib: this version will no longer work once we update ARM's CpuDxe to depend on the ARM specific version. Since this module does not actually rely on it, let's just remove all mention of it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
2016-03-17BeagleBoardPkg: move to ARM version of CpuExceptionHandlerLibArd Biesheuvel1-1/+1
Change our resolution for the previously unused CpuExceptionHandlerLib from the null implementation to the newly added implementation specific to AARCH64 and ARM. This is needed since our CpuDxe will start using it in a subsequent patch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
2016-03-17ArmVirtPkg/ArmVirtQemu: move to ARM version of CpuExceptionHandlerLibArd Biesheuvel1-1/+1
Change our resolution for the previously unused CpuExceptionHandlerLib from the null implementation to the newly added implementation specific to AARCH64 and ARM. This is needed since our CpuDxe will start using it in a subsequent patch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com>
2016-03-17ShellPkg: Remove the unused local variable.Qiu Shumin1-3/+0
Remove the unused local variable to refine the code. Cc: Jaben Carsey <jaben.carsey@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc:Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-03-17MdeModulePkg: Fixed incorrect return value of MatchStringCecil Sheng1-5/+29
In UEFI2.6, CapturePtr's in the Captures array returned by MatchString are to be separatedly allocated so that they can be freed by the caller. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Cecil Sheng <cecil.sheng@hpe.com> Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-03-16MdeModulePkg: ConSplitterDxe: use U64 mult/div wrappers in AbsPtr scalingLaszlo Ersek1-3/+24
This is an emergency fix for UINT64 multiplications and divisions not being done with the right BaseLib functions -- they break Ia32 builds. Fixes: 30ed3422ab2de03abf7c1433ebb482f6e5e16f45 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com>
2016-03-16ArmPkg: ARM/AArch64 implementation of CpuExceptionHandlerLibCohen, Eugene9-0/+1577
Introduce ARM and AArch64 instances of the CpuExceptionHandlerLib which provides exception handling and registration of handlers regardless of execution phase. Two variants of the ArmExceptionLib are provided: one where exception handlers reside within the module (meeting appropriate architectural alignment requirements for the vector table) and another one that will relocate a copy of thee xception handlers to an address specified by PcdCpuVectorBaseAddress. The ArmRelocateExceptionLib is intended for use in cases where ArmExceptionLib is too large for the application (uncompressed XIP images) as driven by the vector table alignment padding. The AArch64 build of this library supports execution at EL1, EL2, and EL3 exception levels. Tested on ARM, and AArch64 with SEC, DXE Core, and CpuDxe modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-03-16ArmPkg/ArmLib: add ArmReadHcr to enable read-modify-write of HCRCohen, Eugene2-0/+11
Add ArmReadHcr() to ArmLib to enable read-modify-write of the HCR system register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-03-16MdeModulePkg: Rescale ConSplitter Absolute Pointer.Derek Lin1-7/+36
ConSplitter's Absolute Pointer should scale virtual device's resolution like what Simple Pointer do. Before this change, caller will get Virtual device's resolution but physical device's current point. This change let caller get Virtual device's resolution with virtual device's current point. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Derek Lin <derek.lin2@hpe.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-03-16ShellPkg: Per UEFI Shell 2.2 SPEC to make Shell supports 'NoNesting'.Qiu Shumin3-25/+162
This patch makes Shell support -nonesting invocation option. This option specifies that EFI_SHELL_PROTOCOL.Execute API nesting of a new Shell instance is optional and dependent on the 'nonesting' Shell environment variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Jim Dailey <Jim_Dailey@Dell.com>
2016-03-16NetworkPkg: Fix the driver model issue in HTTP Boot driver.Fu Siyuan6-41/+29
The HTTP Boot driver have some UEFI driver model problems which will make the code ASSERT when it's disconnected. First, the driver opens the HttpSb protocol BY_CHILD without BY_DRIVER attribute. So the driver binding stop won't be called when HTTP driver is disconnected, so a child handle is left and made HTTP driver binding stop function goes into error. This patch remove this unnecessary OpenProtocol and only unload the HII from when both the IP4 and IP6 stack have been stopped completely. The second issue is the HTTP boot driver always use the driver's image handle as it's driver binding handle, it's not correct. HTTP Boot driver provides 2 separate driver binding protocols from IP4 and IP6 stack, so it has 2 driver binding handle. So this patch fix the code to use correct driver binding handle when create/open a HTTP child handle. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
2016-03-16MdeModulePkg: Coding style update for DxeHttpLib.infJiaxin Wu1-2/+2
Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Zhang Lubo <lubo.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Zhang Lubo <lubo.zhang@intel.com>
2016-03-16IntelFrameworkModulePkg/LegacyBootMaintUiLib: Refine the codeDandan Bi1-5/+25
Remove the ASSERT code that may be triggered in LegacyBootMaintUiLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-03-16MdeModulePkg: Refine the UI codeDandan Bi4-71/+17
Remove the ASSERT in UI code that may be triggered, and clean up the useless code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-03-16MdeModulePkg/DriverSampleDxe: Uninstall the ConfigAccess protocolDandan Bi1-0/+2
In DriverSampleInit, has installed the configAccess protocol to the DriverHandle[1], but don't uninstall it in DriverSampleUnload. Now uninstall the configAccess protocol. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-03-16BaseTools: add new command line option to support override PCD valueYonghong Zhu6-16/+156
this patch add new feature to support override PCD value on the command line. The value from the command line is the highest priority. 1.Add option(--pcd) to support both PcdName and TokenSpaceGuild.PcdName 2.For void* type PCD, use following format: cstring PCD: --pcd PcdName="string" unicodestring PCD: --pcd PcdName=L"string" CArray PCD: --pcd PcdName=B"{0x1, 0x2}" 3.Build Report, use *B to show the PCD value was overridden in the command line. 4.Error Condition: Report error if the PCD is not found Report error if the PcdName is found under multiple different TokenSpaceGuid Report error if PCD value syntax is incorrect Report error if void* type PCD value exceed its max size Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-15OvmfPkg/LegacyRegion: Support legacy region manipulation of Q35Ruiyu Ni2-39/+87
Current implementation only supports legacy region of 440 chip. When QEMU is launched in Q35 mode using CSM enabled OVMF image, LegacyBios driver fails to start due to the legacy region [0xC0000, 0xFFFFF] cannot be written. v2: * just updates the comments. v3: * uses PcdOvmfHostBridgePciDevId as Jordan suggested. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Justen Jordan <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-15BaseTools: Support recent versions of cx_freeze.Marvin Haeuser1-1/+1
This patch fixes the assumed invalid command to start recent versions of cx_freeze on Windows, which are python and not Windows executables. To launch them correctly, the '$(PYTHON_HOME)\python' prefix has been added, so that Python can interpret the tool. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-03-15BaseTools: Add two macros into AutoGenObject macro dictYonghong Zhu1-0/+2
Add DEST_DIR_OUTPUT and DEST_DIR_DEBUG into AutoGenObject macro dict. Because some module (eg: BaseUefiCpuLib) may use this macro in the make file. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-15BaseTools: Mentioned get_vsvars.bat at ReadMePeter Kirmeier1-1/+3
When someone doesn't know where to find or what to do with vsvars32.bat, get_vsvars.bat can be used. CC: Yonghong Zhu <yonghong.zhu@intel.com> CC: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peter Kirmeier <topeterk@freenet.de> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-15MdePkg: Add UEFI2.6 HII Image Ex and Image Decoder protocol definition.Cecil Sheng3-0/+448
Add the definition for the new UEFI 2.6 EFI_HII_IMAGE_EX_PROTOCOL and EFI_IMAGE_DECODER_PROTOCOL. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Cecil Sheng <cecil.sheng@hpe.com> Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-03-15MdeModulePkg: Add PcdMaxPeiPerformanceLogEntries16 PROMPT&HELP STR to *.uniStar Zeng1-1/+10
Commit 7c50b3434377cbb49ce4514ee31339000a5cadc0 introduced PcdMaxPeiPerformanceLogEntries16 to support > 256 PEI performance log entries, but its PROMPT&HELP STR were forgotten to be added into *.uni. Commit 7c50b3434377cbb49ce4514ee31339000a5cadc0 also updated PcdMaxPeiPerformanceLogEntries HELP STR. This patch is to add PcdMaxPeiPerformanceLogEntries16 PROMPT&HELP STR and update PcdMaxPeiPerformanceLogEntries HELP STR in *.uni. Cc: Shumin Qiu <shumin.qiu@intel.com> Cc: Cinnamon Shia <cinnamon.shia@hpe.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Shumin Qiu <shumin.qiu@intel.com> Reviewed-by: Cinnamon Shia <cinnamon.shia@hpe.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-03-15NetworkPkg: fix function comments in HttpBootDxe.Fu Siyuan3-2/+4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Zhang Lubo <lubo.zhang@intel.com>
2016-03-15CryptoPkg: Fix the potential system hang issueJiaxin Wu1-12/+17
This patch is used to fix the potential system hang caused by the NULL 'time' parameter usage. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Long Qin <qin.long@intel.com> Cc: Ye Ting <ting.ye@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: David Woodhouse <David.Woodhouse@intel.com>
2016-03-14ArmPlatformPkg: PL061: support multiple controllerHaojian Zhuang3-59/+129
Support multiple PL061 controllers. If platform gpio driver couldn't be found, PL061 gpio driver will continue to load PcdPL061GpioBase as the register base. It could be compatible with the use case of current PL061 gpio driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-03-14EmbeddedPkg: enhance for multiple gpio controllersHaojian Zhuang2-0/+18
EmbeddedGpio only supports one gpio controller in one platform. Now create PLATFORM_GPIO_CONTROLLER to support multiple gpio controllers in one platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-03-14ShellPkg: Fix Shell ASSERT when read 'TAB' key fail from 'ConIn'.Qiu Shumin1-2/+4
Free 'FoundFileList' when read 'TAB' key fail to avoid memory leak and ASSERT. Cc: Jaben Carsey <jaben.carsey@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-03-14BaseTools/BPDG: Fix the bug to get the PCD SizeYonghong Zhu1-15/+15
The original bug is only consider int format of PcdSize, but forgot the Hex format. The fix is use the already exist variable PCD.PcdBinSize which done to translate PCD size cover both format. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-13UefiCpuPkg/Include: Add top level MSR include fileMichael Kinney1-0/+48
Add top level MSR include file that includes the Architecural MSR include file and all family specific MSR files from the Msr subdirectory Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR). Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Pentium MSR include fileMichael Kinney1-0/+121
Add Pentium MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add P6 MSR include fileMichael Kinney1-0/+1608
Add P6 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Pentium M MSR include fileMichael Kinney1-0/+643
Add Pentium M MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-18. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Core Solo/Duo MSR include fileMichael Kinney1-0/+1074
Add Core Solo/Duo MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-17. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Pentium 4 MSR include fileMichael Kinney1-0/+2550
Add Pentium 4 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon Phi MSR include fileMichael Kinney1-0/+1426
Add Xeon Phi MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Skylake MSR include fileMichael Kinney1-0/+1008
Add Skylake MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-14. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon Processor D MSR include fileMichael Kinney1-0/+1430
Add Xeon Processor D MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Broadwell MSR include fileMichael Kinney1-0/+265
Add Broadwell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Haswell-E MSR include fileMichael Kinney1-0/+5995
Add Haswell-E MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Haswell MSR include fileMichael Kinney1-0/+2575
Add Haswell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
generated by cgit v1.1 at 2024-10-02 13:16:38 +0000