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2016-03-17MdeModulePkg: Fixed incorrect return value of MatchStringCecil Sheng1-5/+29
In UEFI2.6, CapturePtr's in the Captures array returned by MatchString are to be separatedly allocated so that they can be freed by the caller. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Cecil Sheng <cecil.sheng@hpe.com> Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-03-16MdeModulePkg: ConSplitterDxe: use U64 mult/div wrappers in AbsPtr scalingLaszlo Ersek1-3/+24
This is an emergency fix for UINT64 multiplications and divisions not being done with the right BaseLib functions -- they break Ia32 builds. Fixes: 30ed3422ab2de03abf7c1433ebb482f6e5e16f45 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com>
2016-03-16ArmPkg: ARM/AArch64 implementation of CpuExceptionHandlerLibCohen, Eugene9-0/+1577
Introduce ARM and AArch64 instances of the CpuExceptionHandlerLib which provides exception handling and registration of handlers regardless of execution phase. Two variants of the ArmExceptionLib are provided: one where exception handlers reside within the module (meeting appropriate architectural alignment requirements for the vector table) and another one that will relocate a copy of thee xception handlers to an address specified by PcdCpuVectorBaseAddress. The ArmRelocateExceptionLib is intended for use in cases where ArmExceptionLib is too large for the application (uncompressed XIP images) as driven by the vector table alignment padding. The AArch64 build of this library supports execution at EL1, EL2, and EL3 exception levels. Tested on ARM, and AArch64 with SEC, DXE Core, and CpuDxe modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-03-16ArmPkg/ArmLib: add ArmReadHcr to enable read-modify-write of HCRCohen, Eugene2-0/+11
Add ArmReadHcr() to ArmLib to enable read-modify-write of the HCR system register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-03-16MdeModulePkg: Rescale ConSplitter Absolute Pointer.Derek Lin1-7/+36
ConSplitter's Absolute Pointer should scale virtual device's resolution like what Simple Pointer do. Before this change, caller will get Virtual device's resolution but physical device's current point. This change let caller get Virtual device's resolution with virtual device's current point. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Derek Lin <derek.lin2@hpe.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-03-16ShellPkg: Per UEFI Shell 2.2 SPEC to make Shell supports 'NoNesting'.Qiu Shumin3-25/+162
This patch makes Shell support -nonesting invocation option. This option specifies that EFI_SHELL_PROTOCOL.Execute API nesting of a new Shell instance is optional and dependent on the 'nonesting' Shell environment variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Jim Dailey <Jim_Dailey@Dell.com>
2016-03-16NetworkPkg: Fix the driver model issue in HTTP Boot driver.Fu Siyuan6-41/+29
The HTTP Boot driver have some UEFI driver model problems which will make the code ASSERT when it's disconnected. First, the driver opens the HttpSb protocol BY_CHILD without BY_DRIVER attribute. So the driver binding stop won't be called when HTTP driver is disconnected, so a child handle is left and made HTTP driver binding stop function goes into error. This patch remove this unnecessary OpenProtocol and only unload the HII from when both the IP4 and IP6 stack have been stopped completely. The second issue is the HTTP boot driver always use the driver's image handle as it's driver binding handle, it's not correct. HTTP Boot driver provides 2 separate driver binding protocols from IP4 and IP6 stack, so it has 2 driver binding handle. So this patch fix the code to use correct driver binding handle when create/open a HTTP child handle. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
2016-03-16MdeModulePkg: Coding style update for DxeHttpLib.infJiaxin Wu1-2/+2
Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Zhang Lubo <lubo.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Zhang Lubo <lubo.zhang@intel.com>
2016-03-16IntelFrameworkModulePkg/LegacyBootMaintUiLib: Refine the codeDandan Bi1-5/+25
Remove the ASSERT code that may be triggered in LegacyBootMaintUiLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-03-16MdeModulePkg: Refine the UI codeDandan Bi4-71/+17
Remove the ASSERT in UI code that may be triggered, and clean up the useless code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-03-16MdeModulePkg/DriverSampleDxe: Uninstall the ConfigAccess protocolDandan Bi1-0/+2
In DriverSampleInit, has installed the configAccess protocol to the DriverHandle[1], but don't uninstall it in DriverSampleUnload. Now uninstall the configAccess protocol. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-03-16BaseTools: add new command line option to support override PCD valueYonghong Zhu6-16/+156
this patch add new feature to support override PCD value on the command line. The value from the command line is the highest priority. 1.Add option(--pcd) to support both PcdName and TokenSpaceGuild.PcdName 2.For void* type PCD, use following format: cstring PCD: --pcd PcdName="string" unicodestring PCD: --pcd PcdName=L"string" CArray PCD: --pcd PcdName=B"{0x1, 0x2}" 3.Build Report, use *B to show the PCD value was overridden in the command line. 4.Error Condition: Report error if the PCD is not found Report error if the PcdName is found under multiple different TokenSpaceGuid Report error if PCD value syntax is incorrect Report error if void* type PCD value exceed its max size Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-15OvmfPkg/LegacyRegion: Support legacy region manipulation of Q35Ruiyu Ni2-39/+87
Current implementation only supports legacy region of 440 chip. When QEMU is launched in Q35 mode using CSM enabled OVMF image, LegacyBios driver fails to start due to the legacy region [0xC0000, 0xFFFFF] cannot be written. v2: * just updates the comments. v3: * uses PcdOvmfHostBridgePciDevId as Jordan suggested. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Justen Jordan <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-15BaseTools: Support recent versions of cx_freeze.Marvin Haeuser1-1/+1
This patch fixes the assumed invalid command to start recent versions of cx_freeze on Windows, which are python and not Windows executables. To launch them correctly, the '$(PYTHON_HOME)\python' prefix has been added, so that Python can interpret the tool. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-03-15BaseTools: Add two macros into AutoGenObject macro dictYonghong Zhu1-0/+2
Add DEST_DIR_OUTPUT and DEST_DIR_DEBUG into AutoGenObject macro dict. Because some module (eg: BaseUefiCpuLib) may use this macro in the make file. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-15BaseTools: Mentioned get_vsvars.bat at ReadMePeter Kirmeier1-1/+3
When someone doesn't know where to find or what to do with vsvars32.bat, get_vsvars.bat can be used. CC: Yonghong Zhu <yonghong.zhu@intel.com> CC: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peter Kirmeier <topeterk@freenet.de> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-15MdePkg: Add UEFI2.6 HII Image Ex and Image Decoder protocol definition.Cecil Sheng3-0/+448
Add the definition for the new UEFI 2.6 EFI_HII_IMAGE_EX_PROTOCOL and EFI_IMAGE_DECODER_PROTOCOL. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Cecil Sheng <cecil.sheng@hpe.com> Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-03-15MdeModulePkg: Add PcdMaxPeiPerformanceLogEntries16 PROMPT&HELP STR to *.uniStar Zeng1-1/+10
Commit 7c50b3434377cbb49ce4514ee31339000a5cadc0 introduced PcdMaxPeiPerformanceLogEntries16 to support > 256 PEI performance log entries, but its PROMPT&HELP STR were forgotten to be added into *.uni. Commit 7c50b3434377cbb49ce4514ee31339000a5cadc0 also updated PcdMaxPeiPerformanceLogEntries HELP STR. This patch is to add PcdMaxPeiPerformanceLogEntries16 PROMPT&HELP STR and update PcdMaxPeiPerformanceLogEntries HELP STR in *.uni. Cc: Shumin Qiu <shumin.qiu@intel.com> Cc: Cinnamon Shia <cinnamon.shia@hpe.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Shumin Qiu <shumin.qiu@intel.com> Reviewed-by: Cinnamon Shia <cinnamon.shia@hpe.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-03-15NetworkPkg: fix function comments in HttpBootDxe.Fu Siyuan3-2/+4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Zhang Lubo <lubo.zhang@intel.com>
2016-03-15CryptoPkg: Fix the potential system hang issueJiaxin Wu1-12/+17
This patch is used to fix the potential system hang caused by the NULL 'time' parameter usage. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Long Qin <qin.long@intel.com> Cc: Ye Ting <ting.ye@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: David Woodhouse <David.Woodhouse@intel.com>
2016-03-14ArmPlatformPkg: PL061: support multiple controllerHaojian Zhuang3-59/+129
Support multiple PL061 controllers. If platform gpio driver couldn't be found, PL061 gpio driver will continue to load PcdPL061GpioBase as the register base. It could be compatible with the use case of current PL061 gpio driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-03-14EmbeddedPkg: enhance for multiple gpio controllersHaojian Zhuang2-0/+18
EmbeddedGpio only supports one gpio controller in one platform. Now create PLATFORM_GPIO_CONTROLLER to support multiple gpio controllers in one platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-03-14ShellPkg: Fix Shell ASSERT when read 'TAB' key fail from 'ConIn'.Qiu Shumin1-2/+4
Free 'FoundFileList' when read 'TAB' key fail to avoid memory leak and ASSERT. Cc: Jaben Carsey <jaben.carsey@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-03-14BaseTools/BPDG: Fix the bug to get the PCD SizeYonghong Zhu1-15/+15
The original bug is only consider int format of PcdSize, but forgot the Hex format. The fix is use the already exist variable PCD.PcdBinSize which done to translate PCD size cover both format. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-13UefiCpuPkg/Include: Add top level MSR include fileMichael Kinney1-0/+48
Add top level MSR include file that includes the Architecural MSR include file and all family specific MSR files from the Msr subdirectory Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR). Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Pentium MSR include fileMichael Kinney1-0/+121
Add Pentium MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add P6 MSR include fileMichael Kinney1-0/+1608
Add P6 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Pentium M MSR include fileMichael Kinney1-0/+643
Add Pentium M MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-18. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Core Solo/Duo MSR include fileMichael Kinney1-0/+1074
Add Core Solo/Duo MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-17. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Pentium 4 MSR include fileMichael Kinney1-0/+2550
Add Pentium 4 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon Phi MSR include fileMichael Kinney1-0/+1426
Add Xeon Phi MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Skylake MSR include fileMichael Kinney1-0/+1008
Add Skylake MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-14. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon Processor D MSR include fileMichael Kinney1-0/+1430
Add Xeon Processor D MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Broadwell MSR include fileMichael Kinney1-0/+265
Add Broadwell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Haswell-E MSR include fileMichael Kinney1-0/+5995
Add Haswell-E MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Haswell MSR include fileMichael Kinney1-0/+2575
Add Haswell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Ivy Bridge MSR include fileMichael Kinney1-0/+2830
Add Ivy Bridge MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Sandy Bridge MSR include fileMichael Kinney1-0/+4703
Add Sandy Bridge MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon E7 MSR include fileMichael Kinney1-0/+254
Add Xeon E7 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon 5600 MSR include fileMichael Kinney1-0/+182
Add Xeon 5600 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Nehalem MSR include fileMichael Kinney1-0/+7196
Add Nehalem MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Silvermont MSR include fileMichael Kinney1-0/+1468
Add Silvermont MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Atom MSR include fileMichael Kinney1-0/+878
Add Atom MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Core 2 MSR include fileMichael Kinney1-0/+1325
Add Core 2 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Architectural MSR include fileMichael Kinney1-0/+5801
Add Architectural MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-11CryptoPkg/OpensslLib: Upgrade OpenSSL version to 1.0.2gQin Long7-79/+56
OpenSSL 1.0.2g was released with several severity fixes at 01-Mar-2016(https://www.openssl.org/news/secadv/20160301.txt). Upgrade the supported OpenSSL version in CryptoPkg/OpensslLib to catch the latest release 1.0.2g. (NOTE: RT4175 from David Woodhouse was included in 1.0.2g. The new-generated patch will remove this part. And the line endings were still kept as before in this version for consistency) CC: Ting Ye <ting.ye@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Qin Long <qin.long@intel.com> Reviewed-by: David Woodhouse <David.Woodhouse@intel.com>
2016-03-11CryptoPkg/OpensslLib: Convert saved opensslconf.h to DOS line endingsDavid Woodhouse1-2/+3
Until we fix the git repository to store line endings properly and then just check them out in the appropriate form for the platform, let's make process_files.sh convert the opensslconf.h to DOS line endings when it creates it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Reviewed-by: Qin Long <qin.long@intel.com>
2016-03-11ArmVirtPkg/VirtFdtDxe: set /chosen/linux,pci-probe-only to 1 in DTBArd Biesheuvel1-0/+26
Unlike Linux on x86, which typically honors the PCI configuration performed by the firmware, Linux on ARM assumes that the PCI subsystem needs to be configured from scratch. This is not entirely unreasonable given the historical background of embedded systems using very basic bootloaders, but is no longer tenable with Linux on arm64 moving to UEFI and ACPI in the server space. For this reason, PCI support in the arm64 kernel running under ACPI is likely to move to the x86 model of honoring the PCI configuration done by the firmware. So let's align with that in our DT based configuration as well, and set the /chosen/linux,pci-probe-only property to 1 in the Device Tree before we hand it to the OS. In case we are exposing an emulated VGA PCI device to the guest, which may subsequently get exposed via the Graphics Output protocol and driven as an efifb by the OS, this ensures the PCI resource allocations for the framebuffer are not overridden, since that would cause the framebuffer to stop working. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-03-11SecurityPkg: Clear LocalAuthSession content after use.Jiewen Yao1-2/+6
Some commands in DxeTcg2PhysicalPresenceLib accept AuthSession as input parameter and copy to local command buffer. After use, this AuthSession content should be zeroed, because there might be some secrete there. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Zhang, Chao B" <chao.b.zhang@intel.com>
2016-03-11SecurityPkg: Add Tpm2 prefix to lib to avoid conflict.Jiewen Yao1-9/+9
Tpm2Ptp.c is library, but it miss Tpm2 prefix for IsPtpPresence() and GetPtpInterface(). There might be risk as name symbol conflict. This patch adds Tpm2 prefix for them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Zhang, Chao B" <chao.b.zhang@intel.com> Tested-by: "Wu, Hao A" <hao.a.wu@intel.com>
generated by cgit v1.1 at 2024-10-11 15:35:13 +0000