summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2018-05-11SourceLevelDebugPkg/DebugCommLibUsb3: Remove IntelFrameworkPkg.decStar Zeng2-3/+1
Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit 9c6a26d6430f7ca10e6e79e6c9145cbd319944ca)
2018-05-11SourceLevelDebugPkg/DebugCommLibUsb3Pei: Make sure alloc physical memStar Zeng2-9/+24
PI 1.6 has supported pre permanent memory page allocation, to make sure the allocated memory is physical memory for DMA, the patch is to check memory discovered PPI installed or not first before calling AllocatePages. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit 364f63c06533a4de83e6f35ee698700bb24f735f)
2018-05-10IntelFramdworkModulePkg/LegacyBios: Add IoMmu Support.Jiewen Yao3-1/+73
If IOMMU is enabled, the legacy BIOS need allow the legacy memory access by the legacy device. The legacy memory is below 1M memory and HighPmm memory. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 60794ee6b0c86c103ab227b0d9c2968c9c74810e)
2018-05-10IntelSiliconPkg/Vtd: Add more debug info.Jiewen Yao1-1/+1
Add more debug info for reason code. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 8d8c487fb9845685a2d7d0489bc0e2b3cca4d5ff)
2018-05-10IntelSiliconPkg/Vtd: Add missing dump in ExtContext.Jiewen Yao1-0/+1
Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 224f87932d8cd8a585fa335cdb005fbd05ac3004)
2018-05-10IntelSiliconPkg/Vtd: Add DMA_CTRL_PLATFORM_OPT_IN_FLAG dumpJiewen Yao2-0/+8
Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 6cea3c1b51148c34892d03a87e9cb5f253f98b3c)
2018-05-10IntelSiliconPkg/Vtd: Add MapHandleInfo in VtdDxe.Jiewen Yao2-13/+144
This information is to record which device requested which DMA buffer. It can be used for DMA buffer analysis. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 6d2d2e6e5b6619dd46d944b90629739c97ee8a65)
2018-05-10IntelSiliconPkg VTdPmrPei: Add PcdVTdPeiDmaBufferSize(S3)Star Zeng3-7/+22
Add PcdVTdPeiDmaBufferSize(S3) to replace the hard coded value TOTAL_DMA_BUFFER_SIZE and TOTAL_DMA_BUFFER_SIZE_S3 in IntelVTdPmrPei. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 339cb0af96f768bfefee81bf7995a608adeb2125)
2018-05-10IntelSiliconPkg VTdPmrPei: Return SUCCESS when Mapping == NULL in UnmapStar Zeng1-2/+2
NULL is returned to Mapping when Operation is BusMasterCommonBuffer or BusMasterCommonBuffer64 in PeiIoMmuMap(). So Mapping == NULL is valid when calling PeiIoMmuUnmap(). 940dbd071e9f01717236af236740aa0da716805f wrongly changed EFI_SUCCESS to EFI_INVALID_PARAMETER when Mapping == NULL in PeiIoMmuUnmap(). This patch is to correct it. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit abe63fa7dc0de3e1875139a4abd62357795f52d7)
2018-05-10IntelSiliconPkg IntelVTdPmrPei: Install IOMMU PPI for pre-memory phaseStar Zeng1-11/+66
Install IOMMU PPI for pre-memory phase and return EFI_NOT_AVAILABLE_YET to indicate that DMA protection has been enabled, but DMA buffer are not available to be allocated yet. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 940dbd071e9f01717236af236740aa0da716805f)
2018-05-10IntelSiliconPkg IntelVTdPmrPei: Install IoMmu PPI before enabling PMRStar Zeng1-34/+29
Then the consumer of IoMmu PPI has opportunity to get granted DMA buffer (by callback) to replace old buffer before it is forbidden by enabling PMR. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit ed0e52fc9a533fa809c56afbdfd7c350f17e22cc)
2018-05-10IntelSiliconPkg PlatformVTdSampleDxe: State it is only for dev/debugStar Zeng2-2/+8
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 17ac6b23dc92c9a052a252055bec46c70a4b16ee)
2018-05-10IntelSiliconPkg IntelVTdDxe: Fix flush cache issueStar Zeng1-4/+9
The patch fixes flush cache issue in CreateSecondLevelPagingEntryTable(). We found some video cards still not work even they have been added to the exception list. In CreateSecondLevelPagingEntryTable(), the check "(BaseAddress >= MemoryLimit)" may be TRUE and "goto Done" will be executed, then the FlushPageTableMemory operations at the end of the function will be skipped. Instead of "goto Done", this patch uses "break" to break the for loops, then the FlushPageTableMemory operations at the end of the function could have opportunity to be executed. The patch also fixes a miscalculation for Lvl3End. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit bac7f02365b1d24cc6ac93fe853a25ebb8df6efe)
2018-05-10IntelSiliconPkg IntelVTdDxe: Fix DMA does not work issueStar Zeng1-3/+7
Fix DMA does not work issue when system memory is not greater than 4G. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 1d4c17a6ef1a06023cb533d108556c419bdb1fed)
2018-05-10IntelSiliconPkg IntelVTdPmrPei: Get high top by host address widthStar Zeng3-178/+5
Get high top by host address width instead of resource HOB. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit b2725f57c7a1e6feeb176f1563a4f1a8c2eb6c6f)
2018-05-10IntelSiliconPkg IntelVTdDxe: Remove mVtdHostAddressWidthMaskStar Zeng3-5/+1
mVtdHostAddressWidthMask is not been used at all, its definition and related code could be removed. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 9eaa902a52ec1ab0032d0c5a23f9d16493bcb4c5)
2018-05-10IntelSiliconPkg IntelVTdPmrPei: Use HostAddressWidth in DMAR correctlyStar Zeng1-1/+1
According to VTd spec, HostAddressWidth + 1 should be used as the real host address width value. Host Address Width: This field indicates the maximum DMA physical addressability supported by this platform. The system address map reported by the BIOS indicates what portions of this addresses are populated. The Host Address Width (HAW) of the platform is computed as (N+1), where N is the value reported in this field. For example, for a platform supporting 40 bits of physical addressability, the value of 100111b is reported in this field. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 9dd8b1908e7d0585ba6b77d4586f6091842d925c)
2018-05-10IntelSiliconPkg IntelVTdPmrPei: Refine comments about PHMR/PLMR.LimitStar Zeng1-3/+3
According to VTd spec, the real hardware decoded limit should be PHMR/PLMR.Limit value + alignment value. "Bits N:0 of the limit register are decoded by hardware as all 1s." Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit e8097a74b763bfc439c273ddfef8e1d542d83ea7)
2018-05-10IntelSiliconPkg IntelVTdDxe: Fix potential NULL pointer dereferenceStar Zeng1-3/+3
The implementation of MdeModulePkg\Universal\Acpi\AcpiTableDxe reserves first entry of RSDT/XSDT to FADT, the first entry value is 0 when FADT is not installed. So the RSDT/XSDT parsing code should check the entry value first before checking the table signature. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 01bd1c98fa83ef4449798fcf206fbd40db97b2d6)
2018-05-10IntelSiliconPkg IntelVTdDxe: Support early SetAttributes()Star Zeng4-3/+202
Support early SetAttributes() before DMAR table is installed. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 0bc94c748bc9b8645dd0566535708d88a5be0fe1)
2018-05-10IntelSiliconPkg IntelVTdDxe: Use TPL to protect list/engine operationStar Zeng4-31/+26
Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 3a71670618dfa463b3377b752858df7964ad038c)
2018-05-10IntelSiliconPkg IntelVTdDxe: Signal AcpiNotificationFunc() initiallyStar Zeng2-4/+15
Signal AcpiNotificationFunc() initially for the case that DMAR table has been installed when creating event. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit dcd39e09ff3dbec468152a32b343e68e6c87f4b6)
2018-05-10IntelSilicon: Correct function description for AllocateBufferStar Zeng3-3/+3
DUAL_ADDRESS_CYCLE is missing in the EFI_UNSUPPORTED return status description. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> (cherry picked from commit 34e18d1758980d2a01a4503e2be6c06eba59c6ec)
2018-05-10IntelSiliconPkg IntelVTdDxe: Do not SetupVtd againStar Zeng3-5/+10
Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Tested-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 7729e3c448a116eb5b6198f0f70355f421df43fa)
2018-05-10IntelSiliconPkg IntelVTdDxe: Use ACPI table event to get DMAR tableStar Zeng4-30/+46
Use ACPI table event to get DMAR table instead of using ACPI SDT notification as ACPI SDT is optional and the default value of PcdInstallAcpiSdtProtocol is FALSE in MdeModulePkg.dec. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit f6f486e7bf7667ca7bcf50d808e056bd5ac7deaf)
2018-05-10IntelSiliconPkg/VtdPeiSample: Add premem support.Jiewen Yao2-35/+201
Before memory is ready, this sample produces one VTd engine. After memory and silicon is initialized, this sample produces both IGD VTd engine and all-rest VTd engine by reinstall the FV_INFO_PPI. This update is to demonstrate how to support pre-mem VTd usage. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit af807bb98682d0b11dc37188d80fb70687ae2512)
2018-05-10IntelSiliconPkg/VtdPmrPei: Add premem support.Jiewen Yao6-596/+1358
Remove memory discovered dependency to support both premem VTD_INFO_PPI and postmem VTD_INFO_PPI. If VTD_INFO_PPI is installed before memory is ready, this driver protects all memory region. If VTD_INFO_PPI is installed or reinstalled after memory is ready, this driver allocates DMA buffer and protect rest. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit a1e7cd0b020ac024015095068b02e03a68edd96c)
2018-05-10IntelSiliconPkg/VTdDxe: return unsupported for exceptionlistJiewen Yao1-2/+3
Since the exception list is not a recommended way, we returns EFI_UNSUPPORTED in the sample code. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit e5d847476ab6386bef4e3c70e76f5d26c606ed5e)
2018-05-10IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.Jiewen Yao1-2/+2
Change ExitBootServices TPL to CALLBACK, so that a device can disable BME before IOMMU grants access right. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 01df510319f3de8eb358e400dae786cddc160180)
2018-05-10IntelSiliconPkg IntelVTdDxe: use gEfiAcpi10TableGuid for ACPI 1.0Star Zeng2-2/+2
According to definition (Acpi.h and MdePkg.dec), gEfiAcpiTableGuid = gEfiAcpi20TableGuid, and the code is trying to parse ACPI 2.0 first and then ACPI 1.0, but it uses gEfiAcpiTableGuid wrongly for ACPI 1.0, this patch is to fix it. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 118f1657b9c6c338c25ef81e6c30ece392138673)
2018-05-10IntelSiliconPkg/VtdInfoSample: Fix IGD RMRR memory.Jiewen Yao1-1/+1
Fix a calculation problem in IGD RMRR memory. Cc: Zeng Star <zeng.star@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Zeng Star <zeng.star@intel.com> (cherry picked from commit c13cb4aebf4a27dd056f3a4b36d18646ffccef3b)
2018-05-10IntelSiliconPkg/VTdPmrPei: Add EndOfPei callback for S3Jiewen Yao2-2/+59
In S3 resume, before system transfer to waking vector, the VTdPmr need turn off VTd protection based upon VTdPolicy. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit fc8be1ad9ab310b1c7752985c982b66a5a377f1a)
2018-05-10IntelSiliconPkg/dec: Clarify VTdPolicy.Jiewen Yao1-2/+2
Clarify the VTdPolicy is for both PEI and DXE. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 8be3ff8fb82026b6294b1e203563737bfae76a57)
2018-05-10IntelSiliconPkg/VTdDxe: Clean up DXE flush memory.Jiewen Yao2-4/+9
Make sure the context table are flush to memory. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 73a2fe8b871a84c30f77182c3b56c77893488484)
2018-05-10IntelSiliconPkg/VTdInfoSample: Add RMRR table.Jiewen Yao2-10/+149
Let system report RMRR table for the platform support PEI graphic. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 70dc3ec5a72e0e3fc3ea8f63baecdeafd1110db8)
2018-05-10IntelSiliconPkg/IntelVTdPmrPei: Parse RMRR table.Jiewen Yao3-29/+624
In order to support PEI graphic, we let VTdPmrPei driver parse DMAR table RMRR entry and allow the UMA access. If a system has no PEI IGD, no RMRR is needed. The behavior is unchanged. If a system has PEI IGD, it must report RMRR in PEI phase. The PeiVTdPrm will program the IGD VTd engine to skip the RMRR region, and program the rest PCI VTd engine to skip the another DMA buffer allocated in PEI phase for other device driver. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 8e9da4ba3c4a4eeded7651f629330df3a9e5a780)
2018-05-10IntelSiliconPkg/VTdInfoPpi: Let it follow DMAR table.Jiewen Yao1-11/+14
We notice that there is real usage in PEI to show the graphic out. As such we need report RMRR table in PEI to let VTdPmrPei driver skip the IGD UMA region. Now the VTD_INFO PPI uses the same DMAR data structure. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit f02c531967785780ad14fbc8475d8322dfd0909b)
2018-05-10IntelSiliconPkg/VTdPei: Fix Linux build error.Jiewen Yao3-3/+3
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 4084ccfa22dab15e2b9c3f531ba9ec18a6e08a8d)
2018-05-10IntelSiliconPkg/PlatformIntelVTdInfoSamplePei: Move to feature dir.Jiewen Yao5-1/+1
Move PlatformIntelVTdInfoSamplePei to Feature/VTd/. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit bec7a86c70398e774eb90511d7d5a370e23ad0dd)
2018-05-10IntelSiliconPkg/IntelVTdPmrPei: Move to feature dir.Jiewen Yao7-1/+1
Move IntelVTdPmrPei to Feature/VTd/IntelVTdPmrPei. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit db5c75863d17e9fc1e5b7081a7ec62dee8c6f177)
2018-05-10IntelSiliconPkg/PlatformVTdSampleDxe: Move to feature dir.Jiewen Yao5-1/+1
Move PlatformVTdSampleDxe to Feature/VTd/PlatformVTdSampleDxe. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit e4c9ac648d3db26103b778d69b62290863986e82)
2018-05-10IntelSiliconPkg/IntelVTdDxe: Move to feature dir.Jiewen Yao13-1/+1
Move IntelVTdDxe to Feature/VTd/IntelVTdDxe. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 9010459c9aaa985619e341ecc2789a06993b2310)
2018-05-10IntelSiliconPkg/dsc: Add PlatformVTdInfoSamplePei.Jiewen Yao1-0/+1
Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 8a4ed1188b7d3e6d39c9759a6f91fbbc5660160e)
2018-05-10IntelSiliconPkg: Add PlatformVTdInfoSamplePei.Jiewen Yao4-0/+156
This is a sample driver to produce VTD_INFO PPI. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 53269009cbe4bb59520630aef971b89f82a3c72d)
2018-05-10IntelSiliconPkg/dsc: Add IntelVTdPmrPeim.Jiewen Yao1-0/+9
Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 71cfa709ed591ceca36017e93304cce1de51c810)
2018-05-10IntelSiliconPkg: Add IntelVTdPmrPei.Jiewen Yao6-0/+1096
This PEIM is to produce IOMMU_PPI, so that PEI device driver can have better DAM management. This PEIM will setup VTD PMR register to protect most DRAM. It allocates a big chunk DMA buffer in the entrypoint, and only use this buffer for DMA. Any other region is DMA protected. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 3f5ed3fa13c66d66e1a7c5df9a78311f9a0ed991)
2018-05-10IntelSiliconPkg/dec: Add VTD_INFO PPI GUIDJiewen Yao1-0/+3
Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 0b7df50021b9d21c2acef3bc06c683febbbeb60d)
2018-05-10IntelSiliconPkg/include: Add VTD_INFO PPI.Jiewen Yao1-0/+40
This VTD_INFO_PPI is to provide VTD information in PEI. As such, we can have a generic VTd driver. It is a lightweight version DMAR table, but it does not contain PCI device information. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 77562d13ac7fa2c3840ccae598b26e665251ede7)
2018-05-10IntelSiliconPkg/VTdDxe: Disable PMRJiewen Yao1-1/+50
When VTd translation is enabled, PMR can be disable. Or the DMA will be blocked by PMR. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit ffe77707a320077373d35029ba5b43253da6fd05)
2018-05-10IntelSiliconPkg/Vtd.h: Add definition for PMR.Jiewen Yao1-0/+6
Add missing PMR definition in VTd spec. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 40cc2270556ec5e49d184c946bb58981f7155cf3)
generated by cgit v1.1 at 2024-09-17 17:53:11 +0000