UefiCpuPkg/PiSmmCpuDxeSmm: Introduce page table pool mechanism

Introduce page table pool mechanism for smm page table to simplify
page table memory management and protection. This mechanism has been
used in DxeIpl. The basic idea is to allocate a bunch of continuous
pages of memory in advance, and all future page tables consumption
will happen in those pool instead of system memory.
Since we have centralized page tables, we only need to mark all page
table pools as RO, instead of searching page table memory layer by
layer in smm page table. Once current page table pool has been used
up, another memory pool will be allocated and the new pool will also
be set as RO if current page table memory has been marked as RO.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

1 files changed, 2 insertions, 18 deletions

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index bf90050..8d42d89 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -21,24 +21,6 @@ BOOLEAN                   mCpuSmmRestrictedMemoryAccess;
 X86_ASSEMBLY_PATCH_LABEL  gPatch5LevelPagingNeeded;

 

 /**

-  Disable CET.

-**/

-VOID

-EFIAPI

-DisableCet (

-  VOID

-  );

-

-/**

-  Enable CET.

-**/

-VOID

-EFIAPI

-EnableCet (

-  VOID

-  );

-

-/**

   Check if 1-GByte pages is supported by processor or not.

 

   @retval TRUE   1-GByte pages is supported.

@@ -1305,6 +1287,8 @@ SetPageTableAttributes (
     EnableCet ();

   }

 

+  mIsReadOnlyPageTable = TRUE;

+

   return;

 }