UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm

This patch is code refactoring and doesn't change any functionality.
Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. In previous
code, mInternalCr3 is used to pass address of page table which is
different from Cr3 register in different level of SetMemoryAttributes
function. Now remove it and pass the page table base address from the
root function parameter to simplify the code logic.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

1 files changed, 23 insertions, 51 deletions

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index 538394f..6587212 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -18,7 +18,6 @@ extern UINTN  mSmmShadowStackSize;
 LIST_ENTRY                mPagePool           = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool);

 BOOLEAN                   m1GPageTableSupport = FALSE;

 BOOLEAN                   mCpuSmmRestrictedMemoryAccess;

-BOOLEAN                   m5LevelPagingNeeded;

 X86_ASSEMBLY_PATCH_LABEL  gPatch5LevelPagingNeeded;

 

 /**

@@ -114,36 +113,6 @@ Is5LevelPagingNeeded (
 }

 

 /**

-  Get page table base address and the depth of the page table.

-

-  @param[out] Base        Page table base address.

-  @param[out] FiveLevels  TRUE means 5 level paging. FALSE means 4 level paging.

-**/

-VOID

-GetPageTable (

-  OUT UINTN    *Base,

-  OUT BOOLEAN  *FiveLevels OPTIONAL

-  )

-{

-  IA32_CR4  Cr4;

-

-  if (mInternalCr3 == 0) {

-    *Base = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;

-    if (FiveLevels != NULL) {

-      Cr4.UintN   = AsmReadCr4 ();

-      *FiveLevels = (BOOLEAN)(Cr4.Bits.LA57 == 1);

-    }

-

-    return;

-  }

-

-  *Base = mInternalCr3;

-  if (FiveLevels != NULL) {

-    *FiveLevels = m5LevelPagingNeeded;

-  }

-}

-

-/**

   Set sub-entries number in entry.

 

   @param[in, out] Entry        Pointer to entry

@@ -1195,20 +1164,21 @@ SetPageTableAttributes (
   VOID

   )

 {

-  UINTN    Index2;

-  UINTN    Index3;

-  UINTN    Index4;

-  UINTN    Index5;

-  UINT64   *L1PageTable;

-  UINT64   *L2PageTable;

-  UINT64   *L3PageTable;

-  UINT64   *L4PageTable;

-  UINT64   *L5PageTable;

-  UINTN    PageTableBase;

-  BOOLEAN  IsSplitted;

-  BOOLEAN  PageTableSplitted;

-  BOOLEAN  CetEnabled;

-  BOOLEAN  Enable5LevelPaging;

+  UINTN     Index2;

+  UINTN     Index3;

+  UINTN     Index4;

+  UINTN     Index5;

+  UINT64    *L1PageTable;

+  UINT64    *L2PageTable;

+  UINT64    *L3PageTable;

+  UINT64    *L4PageTable;

+  UINT64    *L5PageTable;

+  UINTN     PageTableBase;

+  BOOLEAN   IsSplitted;

+  BOOLEAN   PageTableSplitted;

+  BOOLEAN   CetEnabled;

+  BOOLEAN   Enable5LevelPaging;

+  IA32_CR4  Cr4;

 

   //

   // Don't mark page table memory as read-only if

@@ -1258,11 +1228,13 @@ SetPageTableAttributes (
     PageTableSplitted = FALSE;

     L5PageTable       = NULL;

 

-    GetPageTable (&PageTableBase, &Enable5LevelPaging);

+    PageTableBase      = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;

+    Cr4.UintN          = AsmReadCr4 ();

+    Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);

 

     if (Enable5LevelPaging) {

       L5PageTable = (UINT64 *)PageTableBase;

-      SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);

+      SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);

       PageTableSplitted = (PageTableSplitted || IsSplitted);

     }

 

@@ -1276,7 +1248,7 @@ SetPageTableAttributes (
         L4PageTable = (UINT64 *)PageTableBase;

       }

 

-      SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);

+      SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);

       PageTableSplitted = (PageTableSplitted || IsSplitted);

 

       for (Index4 = 0; Index4 < SIZE_4KB/sizeof (UINT64); Index4++) {

@@ -1285,7 +1257,7 @@ SetPageTableAttributes (
           continue;

         }

 

-        SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);

+        SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);

         PageTableSplitted = (PageTableSplitted || IsSplitted);

 

         for (Index3 = 0; Index3 < SIZE_4KB/sizeof (UINT64); Index3++) {

@@ -1299,7 +1271,7 @@ SetPageTableAttributes (
             continue;

           }

 

-          SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);

+          SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);

           PageTableSplitted = (PageTableSplitted || IsSplitted);

 

           for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {

@@ -1313,7 +1285,7 @@ SetPageTableAttributes (
               continue;

             }

 

-            SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);

+            SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);

             PageTableSplitted = (PageTableSplitted || IsSplitted);

           }

         }