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author | Anthony PERARD <anthony.perard@citrix.com> | 2019-08-13 12:30:50 +0100 |
---|---|---|
committer | Laszlo Ersek <lersek@redhat.com> | 2019-08-21 18:03:49 +0200 |
commit | a8c791c15be599f5a48f8a70b040fbe0cd3232c0 (patch) | |
tree | 2a7ca2c3f9fc6134bca9ed3ab9b6583a5610ba90 /OvmfPkg | |
parent | 1e9d6b0f98b53498f8ae4104502da087493eba2c (diff) | |
download | edk2-a8c791c15be599f5a48f8a70b040fbe0cd3232c0.zip edk2-a8c791c15be599f5a48f8a70b040fbe0cd3232c0.tar.gz edk2-a8c791c15be599f5a48f8a70b040fbe0cd3232c0.tar.bz2 |
OvmfPkg/XenResetVector: Add new entry point for Xen PVH
Add a new entry point for Xen PVH that enter directly in 32bits.
Information on the expected state of the machine when this entry point
is used can be found at:
https://xenbits.xenproject.org/docs/unstable/misc/pvh.html
Also, compare to the original file [1], the two `nop' of the "resetVector"
entry point are removed. There were introduced by 8332983e2e33
("UefiCpuPkg: Replace the un-necessary WBINVD instruction at the reset
vector with two NOPs in VTF0.", 2011-08-04), but don't seems to be
useful. This is the entry point used by HVM guest (hvmloader).
[1] UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1689
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20190813113119.14804-7-anthony.perard@citrix.com>
Diffstat (limited to 'OvmfPkg')
-rw-r--r-- | OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm | 79 | ||||
-rw-r--r-- | OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm | 49 | ||||
-rw-r--r-- | OvmfPkg/XenResetVector/XenResetVector.nasmb | 1 |
3 files changed, 129 insertions, 0 deletions
diff --git a/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm b/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm new file mode 100644 index 0000000..56749bd --- /dev/null +++ b/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm @@ -0,0 +1,79 @@ +;------------------------------------------------------------------------------
+; @file
+; First code executed by processor after resetting.
+;
+; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2019, Citrix Systems, Inc.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+BITS 16
+
+ALIGN 16
+
+;
+; Pad the image size to 4k when page tables are in VTF0
+;
+; If the VTF0 image has page tables built in, then we need to make
+; sure the end of VTF0 is 4k above where the page tables end.
+;
+; This is required so the page tables will be 4k aligned when VTF0 is
+; located just below 0x100000000 (4GB) in the firmware device.
+;
+%ifdef ALIGN_TOP_TO_4K_FOR_PAGING
+ TIMES (0x1000 - ($ - EndOfPageTables) - (fourGigabytes - xenPVHEntryPoint)) DB 0
+%endif
+
+BITS 32
+xenPVHEntryPoint:
+;
+; Entry point to use when running as a Xen PVH guest. (0xffffffd0)
+;
+; Description of the expected state of the machine when this entry point is
+; used can be found at:
+; https://xenbits.xenproject.org/docs/unstable/misc/pvh.html
+;
+ jmp xenPVHMain
+
+BITS 16
+ALIGN 16
+
+applicationProcessorEntryPoint:
+;
+; Application Processors entry point
+;
+; GenFv generates code aligned on a 4k boundary which will jump to this
+; location. (0xffffffe0) This allows the Local APIC Startup IPI to be
+; used to wake up the application processors.
+;
+ jmp EarlyApInitReal16
+
+ALIGN 8
+
+ DD 0
+
+;
+; The VTF signature
+;
+; VTF-0 means that the VTF (Volume Top File) code does not require
+; any fixups.
+;
+vtfSignature:
+ DB 'V', 'T', 'F', 0
+
+ALIGN 16
+
+resetVector:
+;
+; Reset Vector
+;
+; This is where the processor will begin execution
+;
+ jmp EarlyBspInitReal16
+
+ALIGN 16
+
+fourGigabytes:
+
diff --git a/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm b/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm new file mode 100644 index 0000000..2a17fed --- /dev/null +++ b/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm @@ -0,0 +1,49 @@ +;------------------------------------------------------------------------------
+; @file
+; An entry point use by Xen when a guest is started in PVH mode.
+;
+; Copyright (c) 2019, Citrix Systems, Inc.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+BITS 32
+
+xenPVHMain:
+ ;
+ ; 'BP' to indicate boot-strap processor
+ ;
+ mov di, 'BP'
+
+ ;
+ ; ESP will be used as initial value of the EAX register
+ ; in Main.asm
+ ;
+ xor esp, esp
+
+ mov ebx, ADDR_OF(gdtr)
+ lgdt [ebx]
+
+ mov eax, SEC_DEFAULT_CR0
+ mov cr0, eax
+
+ jmp LINEAR_CODE_SEL:ADDR_OF(.jmpToNewCodeSeg)
+.jmpToNewCodeSeg:
+
+ mov eax, SEC_DEFAULT_CR4
+ mov cr4, eax
+
+ mov ax, LINEAR_SEL
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+
+ ;
+ ; Jump to the main routine of the pre-SEC code
+ ; skiping the 16-bit part of the routine and
+ ; into the 32-bit flat mode part
+ ;
+ OneTimeCallRet TransitionFromReal16To32BitFlat
diff --git a/OvmfPkg/XenResetVector/XenResetVector.nasmb b/OvmfPkg/XenResetVector/XenResetVector.nasmb index 89a4b08..0dbc4f2 100644 --- a/OvmfPkg/XenResetVector/XenResetVector.nasmb +++ b/OvmfPkg/XenResetVector/XenResetVector.nasmb @@ -63,6 +63,7 @@ %include "Ia16/Init16.asm"
%include "Main.asm"
+%include "Ia32/XenPVHMain.asm"
%include "Ia16/ResetVectorVtf0.asm"
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