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authorandrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524>2010-02-15 20:40:51 +0000
committerandrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524>2010-02-15 20:40:51 +0000
commit026e30c4bb80a73ac7c5c286711ae07b1c51108b (patch)
tree84fbc585ed86e924d54382baebef00ac7870e891 /Omap35xxPkg
parent95572bd1b8b55fff0b714b3e3a5f923f38eae460 (diff)
downloadedk2-026e30c4bb80a73ac7c5c286711ae07b1c51108b.zip
edk2-026e30c4bb80a73ac7c5c286711ae07b1c51108b.tar.gz
edk2-026e30c4bb80a73ac7c5c286711ae07b1c51108b.tar.bz2
Cleanup SerailIO drivers to have a device path and use PCD settings for various stuff. Also clean up a few coding convention items.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10009 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'Omap35xxPkg')
-rw-r--r--Omap35xxPkg/Flash/Flash.c77
-rw-r--r--Omap35xxPkg/Gpio/Gpio.c4
-rw-r--r--Omap35xxPkg/InterruptDxe/HardwareInterrupt.c24
-rw-r--r--Omap35xxPkg/MMCHSDxe/MMCHS.c26
-rw-r--r--Omap35xxPkg/PciEmulation/PciEmulation.c6
-rw-r--r--Omap35xxPkg/TimerDxe/Timer.c441
6 files changed, 368 insertions, 210 deletions
diff --git a/Omap35xxPkg/Flash/Flash.c b/Omap35xxPkg/Flash/Flash.c
index 698003b..c8c34c9 100644
--- a/Omap35xxPkg/Flash/Flash.c
+++ b/Omap35xxPkg/Flash/Flash.c
@@ -22,21 +22,36 @@ NAND_FLASH_INFO *gNandFlashInfo = NULL;
UINT8 *gEccCode;
UINTN gNum512BytesChunks = 0;
-//
-// Device path for SemiHosting. It contains our autogened Caller ID GUID.
-//
-typedef struct {
- VENDOR_DEVICE_PATH Guid;
- EFI_DEVICE_PATH_PROTOCOL End;
-} FLASH_DEVICE_PATH;
-
-FLASH_DEVICE_PATH gDevicePath = {
- {
- { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },
- EFI_CALLER_ID_GUID
- },
- { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
-};
+//
+
+// Device path for SemiHosting. It contains our autogened Caller ID GUID.
+
+//
+
+typedef struct {
+
+ VENDOR_DEVICE_PATH Guid;
+
+ EFI_DEVICE_PATH_PROTOCOL End;
+
+} FLASH_DEVICE_PATH;
+
+
+
+FLASH_DEVICE_PATH gDevicePath = {
+
+ {
+
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },
+
+ EFI_CALLER_ID_GUID
+
+ },
+
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
+
+};
+
//Actual page address = Column address + Page address + Block address.
@@ -110,26 +125,26 @@ GpmcInit (
)
{
//Enable Smart-idle mode.
- MmioWrite32(GPMC_SYSCONFIG, SMARTIDLEMODE);
+ MmioWrite32 (GPMC_SYSCONFIG, SMARTIDLEMODE);
//Set IRQSTATUS and IRQENABLE to the reset value
- MmioWrite32(GPMC_IRQSTATUS, 0x0);
- MmioWrite32(GPMC_IRQENABLE, 0x0);
+ MmioWrite32 (GPMC_IRQSTATUS, 0x0);
+ MmioWrite32 (GPMC_IRQENABLE, 0x0);
//Disable GPMC timeout control.
- MmioWrite32(GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
+ MmioWrite32 (GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
//Set WRITEPROTECT bit to enable write access.
- MmioWrite32(GPMC_CONFIG, WRITEPROTECT_HIGH);
+ MmioWrite32 (GPMC_CONFIG, WRITEPROTECT_HIGH);
//NOTE: Following GPMC_CONFIGi_0 register settings are taken from u-boot memory dump.
- MmioWrite32(GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
- MmioWrite32(GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
- MmioWrite32(GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
- MmioWrite32(GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
- MmioWrite32(GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
- MmioWrite32(GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
- MmioWrite32(GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
+ MmioWrite32 (GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
+ MmioWrite32 (GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
+ MmioWrite32 (GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
+ MmioWrite32 (GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
+ MmioWrite32 (GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
+ MmioWrite32 (GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
+ MmioWrite32 (GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
}
EFI_STATUS
@@ -215,7 +230,7 @@ NandConfigureEcc (
)
{
//Define ECC size 0 and size 1 to 512 bytes
- MmioWrite32(GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
+ MmioWrite32 (GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
}
VOID
@@ -224,10 +239,10 @@ NandEnableEcc (
)
{
//Clear all the ECC result registers and select ECC result register 1
- MmioWrite32(GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
+ MmioWrite32 (GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
//Enable ECC engine on CS0
- MmioWrite32(GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
+ MmioWrite32 (GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
}
VOID
@@ -236,7 +251,7 @@ NandDisableEcc (
)
{
//Turn off ECC engine.
- MmioWrite32(GPMC_ECC_CONFIG, ECCDISABLE);
+ MmioWrite32 (GPMC_ECC_CONFIG, ECCDISABLE);
}
VOID
diff --git a/Omap35xxPkg/Gpio/Gpio.c b/Omap35xxPkg/Gpio/Gpio.c
index 7bc5478..107c939 100644
--- a/Omap35xxPkg/Gpio/Gpio.c
+++ b/Omap35xxPkg/Gpio/Gpio.c
@@ -79,12 +79,12 @@ Set (
break;
case GPIO_MODE_OUTPUT_0:
- MmioWrite32(ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin));
+ MmioWrite32 (ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin));
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
break;
case GPIO_MODE_OUTPUT_1:
- MmioWrite32(SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin));
+ MmioWrite32 (SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin));
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
break;
diff --git a/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c b/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
index feb5b26..6e30eb7 100644
--- a/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
+++ b/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
@@ -54,10 +54,10 @@ ExitBootServicesEvent (
)
{
// Disable all interrupts
- MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);
- MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);
- MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
+ MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
+ MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
+ MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
}
/**
@@ -125,7 +125,7 @@ EnableInterruptSource (
Bank = Source / 32;
Bit = 1UL << (Source % 32);
- MmioWrite32(INTCPS_MIR_CLEAR(Bank), Bit);
+ MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
return EFI_SUCCESS;
}
@@ -159,7 +159,7 @@ DisableInterruptSource(
Bank = Source / 32;
Bit = 1UL << (Source % 32);
- MmioWrite32(INTCPS_MIR_SET(Bank), Bit);
+ MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
return EFI_SUCCESS;
}
@@ -235,7 +235,7 @@ IrqInterruptHandler (
Vector = MmioRead32(INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;
// Needed to prevent infinite nesting when Time Driver lowers TPL
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
InterruptHandler = gRegisteredInterruptHandlers[Vector];
if (InterruptHandler != NULL) {
@@ -244,7 +244,7 @@ IrqInterruptHandler (
}
// Needed to clear after running the handler
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
}
//
@@ -316,10 +316,10 @@ InterruptDxeInitialize (
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
// Make sure all interrupts are disabled by default.
- MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);
- MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);
- MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
+ MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
+ MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
+ MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
diff --git a/Omap35xxPkg/MMCHSDxe/MMCHS.c b/Omap35xxPkg/MMCHSDxe/MMCHS.c
index 763e1e9..d9739f5 100644
--- a/Omap35xxPkg/MMCHSDxe/MMCHS.c
+++ b/Omap35xxPkg/MMCHSDxe/MMCHS.c
@@ -113,22 +113,22 @@ SendCmd (
while ((MmioRead32(MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED);
//Provide the block size.
- MmioWrite32(MMCHS_BLK, BLEN_512BYTES);
+ MmioWrite32 (MMCHS_BLK, BLEN_512BYTES);
//Setting Data timeout counter value to max value.
MmioAndThenOr32(MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
//Clear Status register.
- MmioWrite32(MMCHS_STAT, 0xFFFFFFFF);
+ MmioWrite32 (MMCHS_STAT, 0xFFFFFFFF);
//Set command argument register
- MmioWrite32(MMCHS_ARG, CmdArgument);
+ MmioWrite32 (MMCHS_ARG, CmdArgument);
//Enable interrupt enable events to occur
- MmioWrite32(MMCHS_IE, CmdInterruptEnableVal);
+ MmioWrite32 (MMCHS_IE, CmdInterruptEnableVal);
//Send a command
- MmioWrite32(MMCHS_CMD, Cmd);
+ MmioWrite32 (MMCHS_CMD, Cmd);
//Check for the command status.
while (RetryCount < MAX_RETRY_COUNT) {
@@ -149,7 +149,7 @@ SendCmd (
//Check if command is completed.
if ((MmcStatus & CC) == CC) {
- MmioWrite32(MMCHS_STAT, CC);
+ MmioWrite32 (MMCHS_STAT, CC);
break;
}
@@ -354,12 +354,12 @@ InitializeMMCHS (
MmioOr32(CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1));
//Software reset of the MMCHS host controller.
- MmioWrite32(MMCHS_SYSCONFIG, SOFTRESET);
+ MmioWrite32 (MMCHS_SYSCONFIG, SOFTRESET);
gBS->Stall(1000);
while ((MmioRead32(MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE);
//Soft reset for all.
- MmioWrite32(MMCHS_SYSCTL, SRA);
+ MmioWrite32 (MMCHS_SYSCTL, SRA);
gBS->Stall(1000);
while ((MmioRead32(MMCHS_SYSCTL) & SRA) != 0x0);
@@ -373,7 +373,7 @@ InitializeMMCHS (
//MMCHS Controller default initialization
MmioOr32(MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF));
- MmioWrite32(MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF));
+ MmioWrite32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF));
//Enable internal clock
MmioOr32(MMCHS_SYSCTL, ICE);
@@ -403,12 +403,12 @@ PerformCardIdenfication (
BOOLEAN SDCmd8Supported = FALSE;
//Enable interrupts.
- MmioWrite32(MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN |
+ MmioWrite32 (MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN |
CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN));
//Controller INIT procedure start.
MmioOr32(MMCHS_CON, INIT);
- MmioWrite32(MMCHS_CMD, 0x00000000);
+ MmioWrite32 (MMCHS_CMD, 0x00000000);
while (!(MmioRead32(MMCHS_STAT) & CC));
//Wait for 1 ms
@@ -418,7 +418,7 @@ PerformCardIdenfication (
MmioOr32(MMCHS_STAT, CC);
//Retry INIT procedure.
- MmioWrite32(MMCHS_CMD, 0x00000000);
+ MmioWrite32 (MMCHS_CMD, 0x00000000);
while (!(MmioRead32(MMCHS_STAT) & CC));
//End initialization sequence
@@ -713,7 +713,7 @@ WriteBlockData(
//Write block worth of data.
for (Count = 0; Count < DataSize; Count++) {
- MmioWrite32(MMCHS_DATA, *DataBuffer++);
+ MmioWrite32 (MMCHS_DATA, *DataBuffer++);
}
break;
diff --git a/Omap35xxPkg/PciEmulation/PciEmulation.c b/Omap35xxPkg/PciEmulation/PciEmulation.c
index fa44570..bdba403 100644
--- a/Omap35xxPkg/PciEmulation/PciEmulation.c
+++ b/Omap35xxPkg/PciEmulation/PciEmulation.c
@@ -63,12 +63,12 @@ ConfigureUSBHost (
UINT8 Data = 0;
// Take USB host out of force-standby mode
- MmioWrite32(UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
+ MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_CLOCKACTIVITY_ON
| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_ENAWAKEUP_ENABLE
| UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
- MmioWrite32(UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
+ MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
@@ -80,7 +80,7 @@ ConfigureUSBHost (
// USB reset (GPIO 147 - Port 5 pin 19) output high
MmioAnd32(GPIO5_BASE + GPIO_OE, ~BIT19);
- MmioWrite32(GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
+ MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
// Get the Power IC protocol.
Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
diff --git a/Omap35xxPkg/TimerDxe/Timer.c b/Omap35xxPkg/TimerDxe/Timer.c
index f43b24b..2753b98 100644
--- a/Omap35xxPkg/TimerDxe/Timer.c
+++ b/Omap35xxPkg/TimerDxe/Timer.c
@@ -54,15 +54,24 @@ volatile UINT32 TIER;
volatile UINTN gVector;
-/**
- C Interrupt Handler calledin the interrupt context when Source interrupt is active.
-
- @param Source Source of the interrupt. Hardware routing off a specific platform defines
- what source means.
- @param SystemContext Pointer to system register context. Mostly used by debuggers and will
- update the system context after the return from the interrupt if
- modified. Don't change these values unless you know what you are doing
-
+/**
+
+ C Interrupt Handler calledin the interrupt context when Source interrupt is active.
+
+
+
+ @param Source Source of the interrupt. Hardware routing off a specific platform defines
+
+ what source means.
+
+ @param SystemContext Pointer to system register context. Mostly used by debuggers and will
+
+ update the system context after the return from the interrupt if
+
+ modified. Don't change these values unless you know what you are doing
+
+
+
**/
VOID
EFIAPI
@@ -71,14 +80,22 @@ TimerInterruptHandler (
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
- EFI_TPL OriginalTPL;
-
- //
- // DXE core uses this callback for the EFI timer tick. The DXE core uses locks
- // that raise to TPL_HIGH and then restore back to current level. Thus we need
- // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
- //
- OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ EFI_TPL OriginalTPL;
+
+
+
+ //
+
+ // DXE core uses this callback for the EFI timer tick. The DXE core uses locks
+
+ // that raise to TPL_HIGH and then restore back to current level. Thus we need
+
+ // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
+
+ //
+
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
if (mTimerPeriodicCallback) {
mTimerPeriodicCallback(SystemContext);
@@ -89,7 +106,7 @@ TimerInterruptHandler (
}
// Clear all timer interrupts
- MmioWrite32(TISR, TISR_CLEAR_ALL);
+ MmioWrite32 (TISR, TISR_CLEAR_ALL);
// Poll interrupt status bits to ensure clearing
while ((MmioRead32(TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
@@ -97,35 +114,64 @@ TimerInterruptHandler (
gBS->RestoreTPL (OriginalTPL);
}
-/**
- This function registers the handler NotifyFunction so it is called every time
- the timer interrupt fires. It also passes the amount of time since the last
- handler call to the NotifyFunction. If NotifyFunction is NULL, then the
- handler is unregistered. If the handler is registered, then EFI_SUCCESS is
- returned. If the CPU does not support registering a timer interrupt handler,
- then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
- when a handler is already registered, then EFI_ALREADY_STARTED is returned.
- If an attempt is made to unregister a handler when a handler is not registered,
- then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
- register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
- is returned.
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param NotifyFunction The function to call when a timer interrupt fires. This
- function executes at TPL_HIGH_LEVEL. The DXE Core will
- register a handler for the timer interrupt, so it can know
- how much time has passed. This information is used to
- signal timer based events. NULL will unregister the handler.
-
- @retval EFI_SUCCESS The timer handler was registered.
- @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
- @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
- registered.
- @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
- previously registered.
- @retval EFI_DEVICE_ERROR The timer handler could not be registered.
-
-**/
+/**
+
+ This function registers the handler NotifyFunction so it is called every time
+
+ the timer interrupt fires. It also passes the amount of time since the last
+
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+
+ returned. If the CPU does not support registering a timer interrupt handler,
+
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
+
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+
+ If an attempt is made to unregister a handler when a handler is not registered,
+
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+
+ is returned.
+
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @param NotifyFunction The function to call when a timer interrupt fires. This
+
+ function executes at TPL_HIGH_LEVEL. The DXE Core will
+
+ register a handler for the timer interrupt, so it can know
+
+ how much time has passed. This information is used to
+
+ signal timer based events. NULL will unregister the handler.
+
+
+
+ @retval EFI_SUCCESS The timer handler was registered.
+
+ @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
+
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
+
+ registered.
+
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+
+ previously registered.
+
+ @retval EFI_DEVICE_ERROR The timer handler could not be registered.
+
+
+
+**/
+
EFI_STATUS
EFIAPI
TimerDriverRegisterHandler (
@@ -146,31 +192,56 @@ TimerDriverRegisterHandler (
return EFI_SUCCESS;
}
-/**
- This function adjusts the period of timer interrupts to the value specified
- by TimerPeriod. If the timer period is updated, then the selected timer
- period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
- the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
- If an error occurs while attempting to update the timer period, then the
- timer hardware will be put back in its state prior to this call, and
- EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
- is disabled. This is not the same as disabling the CPU's interrupts.
- Instead, it must either turn off the timer hardware, or it must adjust the
- interrupt controller so that a CPU interrupt is not generated when the timer
- interrupt fires.
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
- the timer hardware is not programmable, then EFI_UNSUPPORTED is
- returned. If the timer is programmable, then the timer period
- will be rounded up to the nearest timer period that is supported
- by the timer hardware. If TimerPeriod is set to 0, then the
- timer interrupts will be disabled.
-
- @retval EFI_SUCCESS The timer period was changed.
- @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
- @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
-
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+
+ by TimerPeriod. If the timer period is updated, then the selected timer
+
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+
+ If an error occurs while attempting to update the timer period, then the
+
+ timer hardware will be put back in its state prior to this call, and
+
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+
+ is disabled. This is not the same as disabling the CPU's interrupts.
+
+ Instead, it must either turn off the timer hardware, or it must adjust the
+
+ interrupt controller so that a CPU interrupt is not generated when the timer
+
+ interrupt fires.
+
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+
+ returned. If the timer is programmable, then the timer period
+
+ will be rounded up to the nearest timer period that is supported
+
+ by the timer hardware. If TimerPeriod is set to 0, then the
+
+ timer interrupts will be disabled.
+
+
+
+ @retval EFI_SUCCESS The timer period was changed.
+
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+
+
**/
EFI_STATUS
EFIAPI
@@ -185,7 +256,7 @@ TimerDriverSetTimerPeriod (
if (TimerPeriod == 0) {
// Turn off GPTIMER3
- MmioWrite32(TCLR, TCLR_ST_OFF);
+ MmioWrite32 (TCLR, TCLR_ST_OFF);
Status = gInterrupt->DisableInterruptSource(gInterrupt, gVector);
} else {
@@ -194,14 +265,14 @@ TimerDriverSetTimerPeriod (
// Set GPTIMER3 Load register
LoadValue = (INT32) -TimerCount;
- MmioWrite32(TLDR, LoadValue);
- MmioWrite32(TCRR, LoadValue);
+ MmioWrite32 (TLDR, LoadValue);
+ MmioWrite32 (TCRR, LoadValue);
// Enable Overflow interrupt
- MmioWrite32(TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
+ MmioWrite32 (TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
// Turn on GPTIMER3, it will reload at overflow
- MmioWrite32(TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
+ MmioWrite32 (TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
Status = gInterrupt->EnableInterruptSource(gInterrupt, gVector);
}
@@ -214,19 +285,32 @@ TimerDriverSetTimerPeriod (
}
-/**
- This function retrieves the period of timer interrupts in 100 ns units,
- returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
- is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
- returned, then the timer is currently disabled.
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
- 0 is returned, then the timer is currently disabled.
-
- @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
- @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
-
+/**
+
+ This function retrieves the period of timer interrupts in 100 ns units,
+
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+
+ returned, then the timer is currently disabled.
+
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+
+ 0 is returned, then the timer is currently disabled.
+
+
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+
+
**/
EFI_STATUS
EFIAPI
@@ -243,20 +327,34 @@ TimerDriverGetTimerPeriod (
return EFI_SUCCESS;
}
-/**
- This function generates a soft timer interrupt. If the platform does not support soft
- timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
- If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
- service, then a soft timer interrupt will be generated. If the timer interrupt is
- enabled when this service is called, then the registered handler will be invoked. The
- registered handler should not be able to distinguish a hardware-generated timer
- interrupt from a software-generated timer interrupt.
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
-
- @retval EFI_SUCCESS The soft timer interrupt was generated.
- @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
-
+/**
+
+ This function generates a soft timer interrupt. If the platform does not support soft
+
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+
+ service, then a soft timer interrupt will be generated. If the timer interrupt is
+
+ enabled when this service is called, then the registered handler will be invoked. The
+
+ registered handler should not be able to distinguish a hardware-generated timer
+
+ interrupt from a software-generated timer interrupt.
+
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+
+
+ @retval EFI_SUCCESS The soft timer interrupt was generated.
+
+ @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
+
+
+
**/
EFI_STATUS
EFIAPI
@@ -289,39 +387,72 @@ TimerDriverRegisterPeriodicCallback (
}
-/**
- Interface stucture for the Timer Architectural Protocol.
-
- @par Protocol Description:
- This protocol provides the services to initialize a periodic timer
- interrupt, and to register a handler that is called each time the timer
- interrupt fires. It may also provide a service to adjust the rate of the
- periodic timer interrupt. When a timer interrupt occurs, the handler is
- passed the amount of time that has passed since the previous timer
- interrupt.
-
- @param RegisterHandler
- Registers a handler that will be called each time the
- timer interrupt fires. TimerPeriod defines the minimum
- time between timer interrupts, so TimerPeriod will also
- be the minimum time between calls to the registered
- handler.
-
- @param SetTimerPeriod
- Sets the period of the timer interrupt in 100 nS units.
- This function is optional, and may return EFI_UNSUPPORTED.
- If this function is supported, then the timer period will
- be rounded up to the nearest supported timer period.
-
- @param GetTimerPeriod
- Retrieves the period of the timer interrupt in 100 nS units.
-
- @param GenerateSoftInterrupt
- Generates a soft timer interrupt that simulates the firing of
- the timer interrupt. This service can be used to invoke the
- registered handler if the timer interrupt has been masked for
- a period of time.
-
+/**
+
+ Interface stucture for the Timer Architectural Protocol.
+
+
+
+ @par Protocol Description:
+
+ This protocol provides the services to initialize a periodic timer
+
+ interrupt, and to register a handler that is called each time the timer
+
+ interrupt fires. It may also provide a service to adjust the rate of the
+
+ periodic timer interrupt. When a timer interrupt occurs, the handler is
+
+ passed the amount of time that has passed since the previous timer
+
+ interrupt.
+
+
+
+ @param RegisterHandler
+
+ Registers a handler that will be called each time the
+
+ timer interrupt fires. TimerPeriod defines the minimum
+
+ time between timer interrupts, so TimerPeriod will also
+
+ be the minimum time between calls to the registered
+
+ handler.
+
+
+
+ @param SetTimerPeriod
+
+ Sets the period of the timer interrupt in 100 nS units.
+
+ This function is optional, and may return EFI_UNSUPPORTED.
+
+ If this function is supported, then the timer period will
+
+ be rounded up to the nearest supported timer period.
+
+
+
+ @param GetTimerPeriod
+
+ Retrieves the period of the timer interrupt in 100 nS units.
+
+
+
+ @param GenerateSoftInterrupt
+
+ Generates a soft timer interrupt that simulates the firing of
+
+ the timer interrupt. This service can be used to invoke the
+
+ registered handler if the timer interrupt has been masked for
+
+ a period of time.
+
+
+
**/
EFI_TIMER_ARCH_PROTOCOL gTimer = {
TimerDriverRegisterHandler,
@@ -335,18 +466,30 @@ TIMER_DEBUG_SUPPORT_PROTOCOL gTimerDebugSupport = {
};
-/**
- Initialize the state information for the Timer Architectural Protocol and
- the Timer Debug support protocol that allows the debugger to break into a
- running program.
-
- @param ImageHandle of the loaded driver
- @param SystemTable Pointer to the System Table
-
- @retval EFI_SUCCESS Protocol registered
- @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
- @retval EFI_DEVICE_ERROR Hardware problems
-
+/**
+
+ Initialize the state information for the Timer Architectural Protocol and
+
+ the Timer Debug support protocol that allows the debugger to break into a
+
+ running program.
+
+
+
+ @param ImageHandle of the loaded driver
+
+ @param SystemTable Pointer to the System Table
+
+
+
+ @retval EFI_SUCCESS Protocol registered
+
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+
+
**/
EFI_STATUS
EFIAPI