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| author | Dhaval <dhaval@rivosinc.com> | 2024-06-20 17:42:41 +0530 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-07-15 04:05:56 +0000 |
| commit | b54bc983c6102a59c9e0472dd0406ac9ccbaa0bf (patch) | |
| tree | a309d66b733e85f0da70e0872f6be20dc75b47e0 /MdePkg/Include | |
| parent | d4dbe5e101dcb86974f8dce3505b38343b83b432 (diff) | |
| download | edk2-b54bc983c6102a59c9e0472dd0406ac9ccbaa0bf.zip edk2-b54bc983c6102a59c9e0472dd0406ac9ccbaa0bf.tar.gz edk2-b54bc983c6102a59c9e0472dd0406ac9ccbaa0bf.tar.bz2 | |
MdePkg/Library: Add RISCV64 support to BaseRngLib
The ratified RISC-V crypto scalar extensions provide entropy bits via the
seed CSR, as exposed by the Zkr extension. The Zkr extension is ratified
and provides 16 bits of entropy seed when reading the SEED CSR.
Guarded by a RISCV64 Feature PCD, 64-bit random numbers can be
accumulated from the `seed` CSR. This driver is based on the driver in
the Linux kernel.
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Co-authored-by: Tim Wawrzynczak <tim@rivosinc.com>
Diffstat (limited to 'MdePkg/Include')
| -rw-r--r-- | MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index 8ccdea2..a656d44 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -120,4 +120,14 @@ #define CAUSE_VIRTUAL_INST_FAULT 0x16
#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17
+/* Sstc extension */
+#define CSR_SEED 0x15
+
+#define SEED_OPST_MASK 0xc0000000
+#define SEED_OPST_BIST 0x00000000
+#define SEED_OPST_WAIT 0x40000000
+#define SEED_OPST_ES16 0x80000000
+#define SEED_OPST_DEAD 0xc0000000
+#define SEED_ENTROPY_MASK 0xffff
+
#endif
|