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| author | andrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-04-07 18:13:58 +0000 |
|---|---|---|
| committer | andrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-04-07 18:13:58 +0000 |
| commit | 7800c283e0f64417c7d537a99859324ded7eaa7f (patch) | |
| tree | 00e6c0493e416493718527b7ebcce403c4a8cf40 /ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | |
| parent | c5d00b30c1d6bb1198c9d1df30fe9865979253b4 (diff) | |
| download | edk2-7800c283e0f64417c7d537a99859324ded7eaa7f.zip edk2-7800c283e0f64417c7d537a99859324ded7eaa7f.tar.gz edk2-7800c283e0f64417c7d537a99859324ded7eaa7f.tar.bz2 | |
Cleanup Cache an MMU operations.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10348 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm')
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 25 |
1 files changed, 9 insertions, 16 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 72f4ec2..6d65b7e 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -84,17 +84,8 @@ ArmCleanDataCacheEntryBySetWay bx lr -ArmDrainWriteBuffer - mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync - dsb - isb - bx lr - - ArmInvalidateInstructionCache - mov R0,#0 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache - mov R0,#0 dsb isb bx LR @@ -110,15 +101,15 @@ ArmEnableMmu ArmMmuEnabled mrc p15,0,R0,c1,c0,0 and R0,R0,#1 - isb bx LR ArmDisableMmu - mov R0,#0 - mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU mrc p15,0,R0,c1,c0,0 bic R0,R0,#1 mcr p15,0,R0,c1,c0,0 ;Disable MMU + + mcr p15,0,R0,c8,c7,0 ;Invalidate TLB + mcr p15,0,R0,c7,c5,6 ;Invalidate Branch predictor array dsb isb bx LR @@ -127,7 +118,7 @@ ArmEnableDataCache ldr R1,=DC_ON mrc p15,0,R0,c1,c0,0 ;Read control register configuration data orr R0,R0,R1 ;Set C bit - mcr p15,0,r0,c1,c0,0 ;Write control register configuration data + mcr p15,0,R0,c1,c0,0 ;Write control register configuration data dsb isb bx LR @@ -136,7 +127,7 @@ ArmDisableDataCache ldr R1,=DC_ON mrc p15,0,R0,c1,c0,0 ;Read control register configuration data bic R0,R0,R1 ;Clear C bit - mcr p15,0,r0,c1,c0,0 ;Write control register configuration data + mcr p15,0,R0,c1,c0,0 ;Write control register configuration data isb bx LR @@ -144,7 +135,7 @@ ArmEnableInstructionCache ldr R1,=IC_ON mrc p15,0,R0,c1,c0,0 ;Read control register configuration data orr R0,R0,R1 ;Set I bit - mcr p15,0,r0,c1,c0,0 ;Write control register configuration data + mcr p15,0,R0,c1,c0,0 ;Write control register configuration data dsb isb bx LR @@ -153,7 +144,7 @@ ArmDisableInstructionCache ldr R1,=IC_ON mrc p15,0,R0,c1,c0,0 ;Read control register configuration data BIC R0,R0,R1 ;Clear I bit. - mcr p15,0,r0,c1,c0,0 ;Write control register configuration data + mcr p15,0,R0,c1,c0,0 ;Write control register configuration data isb bx LR @@ -217,6 +208,7 @@ Skip bgt Loop1 Finished + dsb ldmfd SP!, {r4-r12, lr} bx LR @@ -226,6 +218,7 @@ ArmDataMemoryBarrier bx LR ArmDataSyncronizationBarrier +ArmDrainWriteBuffer dsb bx LR |