diff options
| author | bxing <bxing@6f19259b-4bc3-4df7-8a09-765794883524> | 2006-05-17 10:22:59 +0000 |
|---|---|---|
| committer | bxing <bxing@6f19259b-4bc3-4df7-8a09-765794883524> | 2006-05-17 10:22:59 +0000 |
| commit | 9f84a60982db062161f0c70827f4d844fa87d472 (patch) | |
| tree | c6bf4297a690d89f2678953239ae10602cebd4b3 | |
| parent | 98fc92fcbd2e63805ace94c908c6ffabe093db5c (diff) | |
| download | edk2-9f84a60982db062161f0c70827f4d844fa87d472.zip edk2-9f84a60982db062161f0c70827f4d844fa87d472.tar.gz edk2-9f84a60982db062161f0c70827f4d844fa87d472.tar.bz2 | |
BaseCacheMaintenanceLib has now been completed on all architectures.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@183 6f19259b-4bc3-4df7-8a09-765794883524
4 files changed, 474 insertions, 10 deletions
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa index 4fd80ab..993c6db 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa @@ -34,6 +34,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. <LibraryClassDefinitions>
<LibraryClass Usage="ALWAYS_PRODUCED">CacheMaintenanceLib</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">BaseLib</LibraryClass>
+ <LibraryClass Usage="ALWAYS_CONSUMED">DebugLib</LibraryClass>
</LibraryClassDefinitions>
<SourceFiles>
<Arch ArchType="IA32">
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c index a7e3623..3a0f6f2 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c @@ -12,6 +12,14 @@ **/
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
VOID
EFIAPI
InvalidateInstructionCache (
@@ -20,6 +28,31 @@ InvalidateInstructionCache ( {
}
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, the no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address
+
+**/
VOID *
EFIAPI
InvalidateInstructionCacheRange (
@@ -27,9 +60,20 @@ InvalidateInstructionCacheRange ( IN UINTN Length
)
{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return Address;
}
+/**
+ Writes Back and Invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes Back and Invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
VOID
EFIAPI
WriteBackInvalidateDataCache (
@@ -38,6 +82,32 @@ WriteBackInvalidateDataCache ( {
}
+/**
+ Writes Back and Invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes Back and Invalidate the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, the no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address
+
+**/
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
@@ -45,9 +115,20 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length
)
{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return Address;
}
+/**
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
VOID
EFIAPI
WriteBackDataCache (
@@ -56,6 +137,31 @@ WriteBackDataCache ( {
}
+/**
+ Writes Back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes Back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, the no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param Length The number of bytes to write back from the data cache.
+
+ @return Address
+
+**/
VOID *
EFIAPI
WriteBackDataCacheRange (
@@ -63,9 +169,21 @@ WriteBackDataCacheRange ( IN UINTN Length
)
{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return Address;
}
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
VOID
EFIAPI
InvalidateDataCache (
@@ -74,6 +192,33 @@ InvalidateDataCache ( {
}
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, the no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param Length The number of bytes to invalidate from the data cache.
+
+ @return Address
+
+**/
VOID *
EFIAPI
InvalidateDataCacheRange (
@@ -81,5 +226,6 @@ InvalidateDataCacheRange ( IN UINTN Length
)
{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return Address;
}
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c index b0d017b..b37ac9e 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c @@ -27,6 +27,14 @@ CallPalProcStatic ( IN UINT64 Arg4
);
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
VOID
EFIAPI
InvalidateInstructionCache (
@@ -36,6 +44,56 @@ InvalidateInstructionCache ( CallPalProcStatic (1, 1, 1, 0);
}
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, the no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address
+
+**/
+VOID*
+EFIAPI
+InvalidateInstructionCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+
+ if (Length > 0) {
+ InvalidateInstructionCache ();
+ }
+ return Address;
+}
+
+/**
+ Writes Back and Invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes Back and Invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
VOID
EFIAPI
WriteBackInvalidateDataCache (
@@ -45,6 +103,32 @@ WriteBackInvalidateDataCache ( CallPalProcStatic (1, 2, 1, 0);
}
+/**
+ Writes Back and Invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes Back and Invalidate the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, the no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address
+
+**/
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
@@ -52,10 +136,24 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length
)
{
- WriteBackInvalidateDataCache ();
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+
+ if (Length > 0) {
+ WriteBackInvalidateDataCache ();
+ }
return Address;
}
+/**
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
VOID
EFIAPI
WriteBackDataCache (
@@ -65,6 +163,31 @@ WriteBackDataCache ( CallPalProcStatic (1, 2, 0, 0);
}
+/**
+ Writes Back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes Back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, the no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param Length The number of bytes to write back from the data cache.
+
+ @return Address
+
+**/
VOID *
EFIAPI
WriteBackDataCacheRange (
@@ -72,18 +195,61 @@ WriteBackDataCacheRange ( IN UINTN Length
)
{
- WriteBackDataCache ();
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+
+ if (Length > 0) {
+ WriteBackDataCache ();
+ }
return Address;
}
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
VOID
EFIAPI
InvalidateDataCache (
VOID
)
{
+ WriteBackInvalidateDataCache ();
}
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, the no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param Length The number of bytes to invalidate from the data cache.
+
+ @return Address
+
+**/
VOID *
EFIAPI
InvalidateDataCacheRange (
@@ -91,5 +257,5 @@ InvalidateDataCacheRange ( IN UINTN Length
)
{
- return Address;
+ return WriteBackInvalidateDataCacheRange (Address, Length);
}
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c b/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c index f86d9d6..3879cdf 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c @@ -14,15 +14,47 @@ **/
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
VOID
EFIAPI
InvalidateInstructionCache (
VOID
)
{
- return;
}
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, the no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address
+
+**/
VOID *
EFIAPI
InvalidateInstructionCacheRange (
@@ -30,9 +62,20 @@ InvalidateInstructionCacheRange ( IN UINTN Length
)
{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return Address;
}
+/**
+ Writes Back and Invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes Back and Invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
VOID
EFIAPI
WriteBackInvalidateDataCache (
@@ -42,6 +85,32 @@ WriteBackInvalidateDataCache ( AsmWbinvd ();
}
+/**
+ Writes Back and Invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes Back and Invalidate the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, the no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address
+
+**/
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
@@ -49,21 +118,66 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length
)
{
- if (Length != 0) {
- AsmWbinvd ();
+ UINT8 (*Uint8Ptr)[32];
+
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+
+ Uint8Ptr = Address;
+ while (Length > sizeof (*Uint8Ptr)) {
+ AsmFlushCacheLine (Uint8Ptr++);
+ Length -= sizeof (*Uint8Ptr);
+ }
+ if (Length > 0) {
+ AsmFlushCacheLine (Uint8Ptr);
+ AsmFlushCacheLine (&(*Uint8Ptr)[Length - 1]);
}
return Address;
}
+/**
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
VOID
EFIAPI
WriteBackDataCache (
VOID
)
{
- AsmWbinvd ();
+ WriteBackInvalidateDataCache ();
}
+/**
+ Writes Back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes Back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, the no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param Length The number of bytes to write back from the data cache.
+
+ @return Address
+
+**/
VOID *
EFIAPI
WriteBackDataCacheRange (
@@ -71,10 +185,20 @@ WriteBackDataCacheRange ( IN UINTN Length
)
{
- AsmWbinvd ();
- return Address;
+ return WriteBackInvalidateDataCacheRange (Address, Length);
}
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
VOID
EFIAPI
InvalidateDataCache (
@@ -84,6 +208,33 @@ InvalidateDataCache ( AsmInvd ();
}
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, the no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param Length The number of bytes to invalidate from the data cache.
+
+ @return Address
+
+**/
VOID *
EFIAPI
InvalidateDataCacheRange (
@@ -91,5 +242,5 @@ InvalidateDataCacheRange ( IN UINTN Length
)
{
- return Address;
+ return WriteBackInvalidateDataCacheRange (Address, Length);
}
|