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authorAndrei Warkentin <andrei.warkentin@intel.com>2023-03-01 10:48:17 -0600
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2023-05-17 23:47:20 +0000
commit0abfb0be6cf78a8e962383e85cec57851ddae5bc (patch)
treecafe81565583677d632029ca70f413350f83bc96
parent45da4e313579f0bcea42062c675c8333d3bad050 (diff)
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OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec
If the SerialPortLib had any initialization needed, this would be skipped in the RiscVVirt Sec. Follow the example seen elsewhere (ArmVirtPkg PrePi). Seen with BaseSerialPortLibRiscVSbiLibRam not using DBCN in Sec, yet using DBCN elsewhere. Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
-rw-r--r--OvmfPkg/RiscVVirt/Sec/SecMain.c4
-rw-r--r--OvmfPkg/RiscVVirt/Sec/SecMain.h1
-rw-r--r--OvmfPkg/RiscVVirt/Sec/SecMain.inf1
3 files changed, 5 insertions, 1 deletions
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c
index b052048..6db39b9 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.c
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c
@@ -1,7 +1,7 @@
/** @file
RISC-V SEC phase module for Qemu Virt.
- Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -57,6 +57,8 @@ SecStartup (
UINT64 StackBase;
UINT32 StackSize;
+ SerialPortInitialize ();
+
//
// Report Status Code to indicate entering SEC core
//
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMain.h
index 83a8058..7c7650f 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.h
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h
@@ -29,6 +29,7 @@
#include <Library/PrePiLib.h>
#include <Library/PlatformInitLib.h>
#include <Library/PrePiHobListPointerLib.h>
+#include <Library/SerialPortLib.h>
#include <Register/RiscV64/RiscVImpl.h>
/**
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
index aed35d3..0e2a578 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
@@ -48,6 +48,7 @@
FdtLib
MemoryAllocationLib
HobLib
+ SerialPortLib
[Ppis]
gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED