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| author | Hao Wu <hao.a.wu@intel.com> | 2018-01-23 12:47:44 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2018-01-24 13:18:09 +0800 |
| commit | 8e6dff048af705bbebf1ee5439942b81d2e08187 (patch) | |
| tree | 7765d6c6d113b1b6e979ea154c85609103ad3e85 | |
| parent | 67a282e0cde51a6e84ab9e309afb578b4968a0ae (diff) | |
| download | edk2-8e6dff048af705bbebf1ee5439942b81d2e08187.zip edk2-8e6dff048af705bbebf1ee5439942b81d2e08187.tar.gz edk2-8e6dff048af705bbebf1ee5439942b81d2e08187.tar.bz2 | |
MdeModulePkg/NvmExpressDxe: Fix data buffer not mapped for Write cmd
Within function NvmExpressPassThru():
The data buffer for the below 2 Admin command:
Create I/O Completion Queue command (Opcode 01h)
Create I/O Submission Queue command (Opcode 05h)
are not mapped to the PCI controller specific addresses.
But the current code logic also prevents the below NVM command:
Write (Opcode 01h)
from mapping its data buffer.
Hence, this commit refine the logic to resolve this issue.
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
(cherry picked from commit 748cd9a68041d00f991eee3570f7150f573d360f)
| -rw-r--r-- | MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c index 7356c1d..302cfdc 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c @@ -3,7 +3,7 @@ NVM Express specification.
(C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
- Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -593,7 +593,8 @@ NvmExpressPassThru ( // these two cmds are special which requires their data buffer must support simultaneous access by both the
// processor and a PCI Bus Master. It's caller's responsbility to ensure this.
//
- if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_CMD) && (Sq->Opc != NVME_ADMIN_CRIOSQ_CMD)) {
+ if (((Sq->Opc & (BIT0 | BIT1)) != 0) &&
+ !((Packet->QueueType == NVME_ADMIN_QUEUE) && ((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD)))) {
if ((Packet->TransferLength == 0) || (Packet->TransferBuffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
|