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author | Jian J Wang <jian.j.wang@intel.com> | 2018-01-15 10:21:08 +0800 |
---|---|---|
committer | Star Zeng <star.zeng@intel.com> | 2018-01-22 09:21:37 +0800 |
commit | 4fd863634abbf62a3c90c0caf599e4a461a12dee (patch) | |
tree | 7128275b978e1a585bbf3ff3654f72cd7f7f1008 | |
parent | 79e67b2967a23cc6d48063c0d5da0440bb4a1fb3 (diff) | |
download | edk2-4fd863634abbf62a3c90c0caf599e4a461a12dee.zip edk2-4fd863634abbf62a3c90c0caf599e4a461a12dee.tar.gz edk2-4fd863634abbf62a3c90c0caf599e4a461a12dee.tar.bz2 |
MdeModulePkg/PiSmmCore: remove NX attr for SMM RAM
If PcdDxeNxMemoryProtectionPolicy is set to enable protection for memory
of EfiReservedMemoryType, the BIOS will hang at a page fault exception
during starting SMM driver.
The root cause is that SMM RAM is type of EfiReservedMemoryType and
marked as non-executable. The fix is simply removing NX attribute for
those memory.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
(cherry picked from commit 94c0129d244f91fa0a7b122414872da49a35f853)
-rw-r--r-- | MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c index a7663ca..94d671b 100644 --- a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c +++ b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c @@ -1550,6 +1550,7 @@ SmmIplEntry ( EFI_CPU_ARCH_PROTOCOL *CpuArch;
EFI_STATUS SetAttrStatus;
EFI_SMRAM_DESCRIPTOR *SmramRangeSmmDriver;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemDesc;
//
// Fill in the image handle of the SMM IPL so the SMM Core can use this as the
@@ -1616,7 +1617,8 @@ SmmIplEntry ( GetSmramCacheRange (mCurrentSmramRange, &mSmramCacheBase, &mSmramCacheSize);
//
- // If CPU AP is present, attempt to set SMRAM cacheability to WB
+ // If CPU AP is present, attempt to set SMRAM cacheability to WB and clear
+ // XP if it's set.
// Note that it is expected that cacheability of SMRAM has been set to WB if CPU AP
// is not available here.
//
@@ -1630,7 +1632,19 @@ SmmIplEntry ( );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "SMM IPL failed to set SMRAM window to EFI_MEMORY_WB\n"));
- }
+ }
+
+ Status = gDS->GetMemorySpaceDescriptor(
+ mCurrentSmramRange->PhysicalStart,
+ &MemDesc
+ );
+ if (!EFI_ERROR (Status) && (MemDesc.Attributes & EFI_MEMORY_XP) != 0) {
+ gDS->SetMemorySpaceAttributes (
+ mCurrentSmramRange->PhysicalStart,
+ mCurrentSmramRange->PhysicalSize,
+ MemDesc.Attributes & (~EFI_MEMORY_XP)
+ );
+ }
}
//
// if Loading module at Fixed Address feature is enabled, save the SMRAM base to Load
|