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authorJiewen Yao <jiewen.yao@intel.com>2017-10-20 16:47:48 +0800
committerStar Zeng <star.zeng@intel.com>2018-05-10 14:23:35 +0800
commit3d06e1898879c46b854338e7e61a6dfc78e60c12 (patch)
tree3e4dbcb18b2e86e348434134a2fa59558b0f5fc9
parent1c8bdffe4f7297bad7a91678e0b486d64f6df505 (diff)
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IntelSiliconPkg/VtdInfoSample: Fix IGD RMRR memory.
Fix a calculation problem in IGD RMRR memory. Cc: Zeng Star <zeng.star@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Zeng Star <zeng.star@intel.com> (cherry picked from commit c13cb4aebf4a27dd056f3a4b36d18646ffccef3b)
-rw-r--r--IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 08a4db3..6267da7 100644
--- a/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ b/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -159,7 +159,7 @@ PatchDmar (
/// Calculate GTT mem size
///
GttMemSize = 0;
- GttMode = PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC) & B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;
+ GttMode = (PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;
if (GttMode <= V_SKL_SA_GGC_GGMS_8MB) {
GttMemSize = (1 << GttMode) * (1024) * (1024);
}