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author | Jussi Pakkanen <jpakkane@gmail.com> | 2017-08-21 22:00:23 +0300 |
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committer | Jussi Pakkanen <jpakkane@gmail.com> | 2018-02-02 20:04:43 +0200 |
commit | 2dfd790f4fb20de40d701cf8a6b39194b9350ee9 (patch) | |
tree | 9927331a7a6849fd4587984fef4b14584c82117e /test cases | |
parent | 0025cb03d27b3f9f7861e176dec9b7a7c56d03db (diff) | |
download | meson-2dfd790f4fb20de40d701cf8a6b39194b9350ee9.zip meson-2dfd790f4fb20de40d701cf8a6b39194b9350ee9.tar.gz meson-2dfd790f4fb20de40d701cf8a6b39194b9350ee9.tar.bz2 |
Created sample project for IceStorm FPGA development.
Diffstat (limited to 'test cases')
-rw-r--r-- | test cases/fpga/1 simple/meson.build | 36 | ||||
-rw-r--r-- | test cases/fpga/1 simple/spin.pcf | 6 | ||||
-rw-r--r-- | test cases/fpga/1 simple/spin.v | 32 |
3 files changed, 74 insertions, 0 deletions
diff --git a/test cases/fpga/1 simple/meson.build b/test cases/fpga/1 simple/meson.build new file mode 100644 index 0000000..ec663f2 --- /dev/null +++ b/test cases/fpga/1 simple/meson.build @@ -0,0 +1,36 @@ +project('lattice', 'c') + +yosys_bin = find_program('yosys') +arachne_bin = find_program('arachne-pnr') +icepack_bin = find_program('icepack') +iceprog_bin = find_program('iceprog') +icetime_bin = find_program('icetime') + +pcffile = files('spin.pcf') + +blif = custom_target('spin_blif', + input : 'spin.v', + output : 'spin.blif', + command : [yosys_bin, '-q', '-p', 'synth_ice40 -blif @OUTPUT@', '@INPUT@'], + ) + +asc = custom_target('spin_asc', + input : blif, + output : 'spin.asc', + command : [arachne_bin, '-q', '-d', '1k', '-p', pcffile, '@INPUT@', '-o', '@OUTPUT@'], + ) + +bin = custom_target('spin-bin', + input : asc, + output : 'spin.bin', + command : [icepack_bin, '@INPUT@', '@OUTPUT@'], + build_by_default : true + ) + +run_target('spin-time', + command : [icetime_bin, '-tmd', 'hx1k', asc], + ) + +run_target('spin-upload', + command : [iceprog_bin, bin] + ) diff --git a/test cases/fpga/1 simple/spin.pcf b/test cases/fpga/1 simple/spin.pcf new file mode 100644 index 0000000..de06f5d --- /dev/null +++ b/test cases/fpga/1 simple/spin.pcf @@ -0,0 +1,6 @@ +set_io LED1 99 +set_io LED2 98 +set_io LED3 97 +set_io LED4 96 +set_io LED5 95 +set_io clk 21 diff --git a/test cases/fpga/1 simple/spin.v b/test cases/fpga/1 simple/spin.v new file mode 100644 index 0000000..edc40c4 --- /dev/null +++ b/test cases/fpga/1 simple/spin.v @@ -0,0 +1,32 @@ + +module top(input clk, output LED1, output LED2, output LED3, output LED4, output LED5); + + reg ready = 0; + reg [23:0] divider; + reg [3:0] spin; + + always @(posedge clk) begin + if (ready) + begin + if (divider == 6000000) + begin + divider <= 0; + spin <= {spin[2], spin[3], spin[0], spin[1]}; + end + else + divider <= divider + 1; + end + else + begin + ready <= 1; + spin <= 4'b1010; + divider <= 0; + end + end + + assign LED1 = spin[0]; + assign LED2 = spin[1]; + assign LED3 = spin[2]; + assign LED4 = spin[3]; + assign LED5 = 1; +endmodule |