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| author | Khem Raj <raj.khem@gmail.com> | 2018-07-14 13:03:39 -0700 |
|---|---|---|
| committer | Nirbheek Chauhan <nirbheek@centricular.com> | 2018-08-24 03:12:55 +0530 |
| commit | 37e01814c6dc9fa23d696e98cc21477e786a5b11 (patch) | |
| tree | 62336be20590f375b48dbf164c211f1789acac20 | |
| parent | 6435445cf30cfe818e2a0e3a50fe42439825b147 (diff) | |
| download | meson-37e01814c6dc9fa23d696e98cc21477e786a5b11.zip meson-37e01814c6dc9fa23d696e98cc21477e786a5b11.tar.gz meson-37e01814c6dc9fa23d696e98cc21477e786a5b11.tar.bz2 | |
mesonbuild: Recognise risc-v architecture
Signed-off-by: Khem Raj <raj.khem@gmail.com>
| -rw-r--r-- | docs/markdown/Reference-tables.md | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/docs/markdown/Reference-tables.md b/docs/markdown/Reference-tables.md index 6486aa2..91a8e3c 100644 --- a/docs/markdown/Reference-tables.md +++ b/docs/markdown/Reference-tables.md @@ -53,6 +53,8 @@ set in the cross file. | ppc64 | 64 bit PPC processors | | e2k | MCST Elbrus processor | | parisc | HP PA-RISC processor | +| riscv32 | 32 bit RISC-V Open ISA| +| riscv64 | 64 bit RISC-V Open ISA| | sparc64 | SPARC v9 processor | Any cpu family not listed in the above list is not guaranteed to |