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# SPDX-License-Identifier: LGPL-2.0+
#
# Sparc instruction decode definitions.
# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
##
## Major Opcodes 00 and 01 -- branches, call, and sethi.
##
&bcc i a cond cc
BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc
FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0
%d16 20:s2 0:14
BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
NCP 00 - ---- 111 ---------------------- # CBcc
SETHI 00 rd:5 100 i:22
CALL 01 i:s30
##
## Major Opcode 10 -- integer, floating-point, vis, and system insns.
##
&r_r_ri rd rs1 rs2_or_imm imm:bool
@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
{
[
STBAR 10 00000 101000 01111 0 0000000000000
MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4
RDCCR 10 rd:5 101000 00010 0 0000000000000
RDASI 10 rd:5 101000 00011 0 0000000000000
RDTICK 10 rd:5 101000 00100 0 0000000000000
RDPC 10 rd:5 101000 00101 0 0000000000000
RDFPRS 10 rd:5 101000 00110 0 0000000000000
RDASR17 10 rd:5 101000 10001 0 0000000000000
RDGSR 10 rd:5 101000 10011 0 0000000000000
RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
RDSTICK 10 rd:5 101000 11000 0 0000000000000
RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000
RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000
]
# Before v8, all rs1 accepted; otherwise rs1==0.
RDY 10 rd:5 101000 rs1:5 0 0000000000000
}
{
[
WRY 10 00000 110000 ..... . ............. @n_r_ri
WRCCR 10 00010 110000 ..... . ............. @n_r_ri
WRASI 10 00011 110000 ..... . ............. @n_r_ri
WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
{
WRGSR 10 10011 110000 ..... . ............. @n_r_ri
WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
}
WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri
WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri
WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri
WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri
WRSTICK 10 11000 110000 ..... . ............. @n_r_ri
WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri
]
# Before v8, rs1==0 was WRY, and the rest executed as nop.
[
NOP_v7 10 ----- 110000 ----- 0 00000000 -----
NOP_v7 10 ----- 110000 ----- 1 -------- -----
]
}
{
RDPSR 10 rd:5 101001 00000 0 0000000000000
RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000
}
RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000
RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000
RDHPR_htba 10 rd:5 101001 00101 0 0000000000000
RDHPR_hver 10 rd:5 101001 00110 0 0000000000000
RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000
{
WRPSR 10 00000 110001 ..... . ............. @n_r_ri
SAVED 10 00000 110001 00000 0 0000000000000
}
RESTORED 10 00001 110001 00000 0 0000000000000
# UA2005 ALLCLEAN
# UA2005 OTHERW
# UA2005 NORMALW
# UA2005 INVALW
{
RDWIM 10 rd:5 101010 00000 0 0000000000000
RDPR_tpc 10 rd:5 101010 00000 0 0000000000000
}
RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000
RDPR_tstate 10 rd:5 101010 00010 0 0000000000000
RDPR_tt 10 rd:5 101010 00011 0 0000000000000
RDPR_tick 10 rd:5 101010 00100 0 0000000000000
RDPR_tba 10 rd:5 101010 00101 0 0000000000000
RDPR_pstate 10 rd:5 101010 00110 0 0000000000000
RDPR_tl 10 rd:5 101010 00111 0 0000000000000
RDPR_pil 10 rd:5 101010 01000 0 0000000000000
RDPR_cwp 10 rd:5 101010 01001 0 0000000000000
RDPR_cansave 10 rd:5 101010 01010 0 0000000000000
RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000
RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000
RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000
RDPR_wstate 10 rd:5 101010 01110 0 0000000000000
RDPR_gl 10 rd:5 101010 10000 0 0000000000000
RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000
RDPR_ver 10 rd:5 101010 11111 0 0000000000000
{
WRWIM 10 00000 110010 ..... . ............. @n_r_ri
WRPR_tpc 10 00000 110010 ..... . ............. @n_r_ri
}
WRPR_tnpc 10 00001 110010 ..... . ............. @n_r_ri
WRPR_tstate 10 00010 110010 ..... . ............. @n_r_ri
WRPR_tt 10 00011 110010 ..... . ............. @n_r_ri
WRPR_tick 10 00100 110010 ..... . ............. @n_r_ri
WRPR_tba 10 00101 110010 ..... . ............. @n_r_ri
WRPR_pstate 10 00110 110010 ..... . ............. @n_r_ri
WRPR_tl 10 00111 110010 ..... . ............. @n_r_ri
WRPR_pil 10 01000 110010 ..... . ............. @n_r_ri
WRPR_cwp 10 01001 110010 ..... . ............. @n_r_ri
WRPR_cansave 10 01010 110010 ..... . ............. @n_r_ri
WRPR_canrestore 10 01011 110010 ..... . ............. @n_r_ri
WRPR_cleanwin 10 01100 110010 ..... . ............. @n_r_ri
WRPR_otherwin 10 01101 110010 ..... . ............. @n_r_ri
WRPR_wstate 10 01110 110010 ..... . ............. @n_r_ri
WRPR_gl 10 10000 110010 ..... . ............. @n_r_ri
WRPR_strand_status 10 11010 110010 ..... . ............. @n_r_ri
{
FLUSHW 10 00000 101011 00000 0 0000000000000
RDTBR 10 rd:5 101011 00000 0 0000000000000
}
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{
# For v7, the entire simm13 field is present, but masked to 7 bits.
# For v8, [12:7] are reserved. However, a compatibility note for
# the Tcc insn in the v9 manual suggests that the v8 reserved field
# was ignored and did not produce traps.
Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7
# For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0).
# Bits [10:8] are reserved and the OSA2011 manual says they must be 0.
Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
}
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