1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
|
/*
* QEMU RISC-V Host Target Interface (HTIF) Emulation
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2017-2018 SiFive, Inc.
*
* This provides HTIF device emulation for QEMU. At the moment this allows
* for identical copies of bbl/linux to run on both spike and QEMU.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "hw/char/riscv_htif.h"
#include "hw/char/serial.h"
#include "chardev/char.h"
#include "chardev/char-fe.h"
#include "qemu/timer.h"
#include "qemu/error-report.h"
#define RISCV_DEBUG_HTIF 0
#define HTIF_DEBUG(fmt, ...) \
do { \
if (RISCV_DEBUG_HTIF) { \
qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\
} \
} while (0)
#define HTIF_DEV_SHIFT 56
#define HTIF_CMD_SHIFT 48
#define HTIF_DEV_SYSTEM 0
#define HTIF_DEV_CONSOLE 1
#define HTIF_SYSTEM_CMD_SYSCALL 0
#define HTIF_CONSOLE_CMD_GETC 0
#define HTIF_CONSOLE_CMD_PUTC 1
static uint64_t fromhost_addr, tohost_addr;
static int address_symbol_set;
void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
uint64_t st_size)
{
if (strcmp("fromhost", st_name) == 0) {
address_symbol_set |= 1;
fromhost_addr = st_value;
if (st_size != 8) {
error_report("HTIF fromhost must be 8 bytes");
exit(1);
}
} else if (strcmp("tohost", st_name) == 0) {
address_symbol_set |= 2;
tohost_addr = st_value;
if (st_size != 8) {
error_report("HTIF tohost must be 8 bytes");
exit(1);
}
}
}
/*
* Called by the char dev to see if HTIF is ready to accept input.
*/
static int htif_can_recv(void *opaque)
{
return 1;
}
/*
* Called by the char dev to supply input to HTIF console.
* We assume that we will receive one character at a time.
*/
static void htif_recv(void *opaque, const uint8_t *buf, int size)
{
HTIFState *htifstate = opaque;
if (size != 1) {
return;
}
/*
* TODO - we need to check whether mfromhost is zero which indicates
* the device is ready to receive. The current implementation
* will drop characters
*/
uint64_t val_written = htifstate->pending_read;
uint64_t resp = 0x100 | *buf;
htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
}
/*
* Called by the char dev to supply special events to the HTIF console.
* Not used for HTIF.
*/
static void htif_event(void *opaque, QEMUChrEvent event)
{
}
static int htif_be_change(void *opaque)
{
HTIFState *s = opaque;
qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
htif_be_change, s, NULL, true);
return 0;
}
/*
* See below the tohost register format.
*
* Bits 63:56 indicate the "device".
* Bits 55:48 indicate the "command".
*
* Device 0 is the syscall device, which is used to emulate Unixy syscalls.
* It only implements command 0, which has two subfunctions:
* - If bit 0 is clear, then bits 47:0 represent a pointer to a struct
* describing the syscall.
* - If bit 1 is set, then bits 47:1 represent an exit code, with a zero
* value indicating success and other values indicating failure.
*
* Device 1 is the blocking character device.
* - Command 0 reads a character
* - Command 1 writes a character from the 8 LSBs of tohost
*
* For RV32, the tohost register is zero-extended, so only device=0 and
* command=0 (i.e. HTIF syscalls/exit codes) are supported.
*/
static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
{
uint8_t device = val_written >> HTIF_DEV_SHIFT;
uint8_t cmd = val_written >> HTIF_CMD_SHIFT;
uint64_t payload = val_written & 0xFFFFFFFFFFFFULL;
int resp = 0;
HTIF_DEBUG("mtohost write: device: %d cmd: %d what: %02" PRIx64
" -payload: %016" PRIx64 "\n", device, cmd, payload & 0xFF, payload);
/*
* Currently, there is a fixed mapping of devices:
* 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy)
* 1: Console
*/
if (unlikely(device == HTIF_DEV_SYSTEM)) {
/* frontend syscall handler, shutdown and exit code support */
if (cmd == HTIF_SYSTEM_CMD_SYSCALL) {
if (payload & 0x1) {
/* exit code */
int exit_code = payload >> 1;
exit(exit_code);
} else {
qemu_log_mask(LOG_UNIMP, "pk syscall proxy not supported\n");
}
} else {
qemu_log("HTIF device %d: unknown command\n", device);
}
} else if (likely(device == HTIF_DEV_CONSOLE)) {
/* HTIF Console */
if (cmd == HTIF_CONSOLE_CMD_GETC) {
/* this should be a queue, but not yet implemented as such */
htifstate->pending_read = val_written;
htifstate->env->mtohost = 0; /* clear to indicate we read */
return;
} else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1);
resp = 0x100 | (uint8_t)payload;
} else {
qemu_log("HTIF device %d: unknown command\n", device);
}
} else {
qemu_log("HTIF unknown device or command\n");
HTIF_DEBUG("device: %d cmd: %d what: %02" PRIx64
" payload: %016" PRIx64, device, cmd, payload & 0xFF, payload);
}
/*
* Latest bbl does not set fromhost to 0 if there is a value in tohost.
* With this code enabled, qemu hangs waiting for fromhost to go to 0.
* With this code disabled, qemu works with bbl priv v1.9.1 and v1.10.
* HTIF needs protocol documentation and a more complete state machine.
*
* while (!htifstate->fromhost_inprogress &&
* htifstate->env->mfromhost != 0x0) {
* }
*/
htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
htifstate->env->mtohost = 0; /* clear to indicate we read */
}
#define TOHOST_OFFSET1 (htifstate->tohost_offset)
#define TOHOST_OFFSET2 (htifstate->tohost_offset + 4)
#define FROMHOST_OFFSET1 (htifstate->fromhost_offset)
#define FROMHOST_OFFSET2 (htifstate->fromhost_offset + 4)
/* CPU wants to read an HTIF register */
static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
{
HTIFState *htifstate = opaque;
if (addr == TOHOST_OFFSET1) {
return htifstate->env->mtohost & 0xFFFFFFFF;
} else if (addr == TOHOST_OFFSET2) {
return (htifstate->env->mtohost >> 32) & 0xFFFFFFFF;
} else if (addr == FROMHOST_OFFSET1) {
return htifstate->env->mfromhost & 0xFFFFFFFF;
} else if (addr == FROMHOST_OFFSET2) {
return (htifstate->env->mfromhost >> 32) & 0xFFFFFFFF;
} else {
qemu_log("Invalid htif read: address %016" PRIx64 "\n",
(uint64_t)addr);
return 0;
}
}
/* CPU wrote to an HTIF register */
static void htif_mm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
HTIFState *htifstate = opaque;
if (addr == TOHOST_OFFSET1) {
if (htifstate->env->mtohost == 0x0) {
htifstate->allow_tohost = 1;
htifstate->env->mtohost = value & 0xFFFFFFFF;
} else {
htifstate->allow_tohost = 0;
}
} else if (addr == TOHOST_OFFSET2) {
if (htifstate->allow_tohost) {
htifstate->env->mtohost |= value << 32;
htif_handle_tohost_write(htifstate, htifstate->env->mtohost);
}
} else if (addr == FROMHOST_OFFSET1) {
htifstate->fromhost_inprogress = 1;
htifstate->env->mfromhost = value & 0xFFFFFFFF;
} else if (addr == FROMHOST_OFFSET2) {
htifstate->env->mfromhost |= value << 32;
htifstate->fromhost_inprogress = 0;
} else {
qemu_log("Invalid htif write: address %016" PRIx64 "\n",
(uint64_t)addr);
}
}
static const MemoryRegionOps htif_mm_ops = {
.read = htif_mm_read,
.write = htif_mm_write,
};
bool htif_uses_elf_symbols(void)
{
return (address_symbol_set == 3) ? true : false;
}
HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env,
Chardev *chr, uint64_t nonelf_base)
{
uint64_t base, size, tohost_offset, fromhost_offset;
if (!htif_uses_elf_symbols()) {
fromhost_addr = nonelf_base;
tohost_addr = nonelf_base + 8;
}
base = MIN(tohost_addr, fromhost_addr);
size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
tohost_offset = tohost_addr - base;
fromhost_offset = fromhost_addr - base;
HTIFState *s = g_new0(HTIFState, 1);
s->env = env;
s->tohost_offset = tohost_offset;
s->fromhost_offset = fromhost_offset;
s->pending_read = 0;
s->allow_tohost = 0;
s->fromhost_inprogress = 0;
qemu_chr_fe_init(&s->chr, chr, &error_abort);
qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
htif_be_change, s, NULL, true);
memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
TYPE_HTIF_UART, size);
memory_region_add_subregion_overlap(address_space, base,
&s->mmio, 1);
return s;
}
|