From 459bb44cc41932a251fdc6cbd18fd0a681cb84e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 15 Jan 2018 13:24:17 +0100 Subject: tests/boot-serial-test: fix powernv support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Recent commit introduced the firmware image skiboot 5.9 which has a different first line ouput. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- tests/boot-serial-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c index 663b78b..418c5b9 100644 --- a/tests/boot-serial-test.c +++ b/tests/boot-serial-test.c @@ -72,7 +72,7 @@ static testdef_t tests[] = { { "ppc64", "ppce500", "", "U-Boot" }, { "ppc64", "prep", "", "Open Hack'Ware BIOS" }, { "ppc64", "pseries", "", "Open Firmware" }, - { "ppc64", "powernv", "-cpu POWER8", "SkiBoot" }, + { "ppc64", "powernv", "-cpu POWER8", "OPAL" }, { "i386", "isapc", "-cpu qemu32 -device sga", "SGABIOS" }, { "i386", "pc", "-device sga", "SGABIOS" }, { "i386", "q35", "-device sga", "SGABIOS" }, -- cgit v1.1 From 83028a2b2871d3787e2fb55fe3e5cd2dda6cc378 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 15 Jan 2018 19:04:01 +0100 Subject: ppc/pnv: use POWER9 DD2 processor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 1ed9c8af501f ("target/ppc: Add POWER9 DD2.0 model information") deprecated the POWER9 model v1.0. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- tests/pnv-xscom-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/pnv-xscom-test.c b/tests/pnv-xscom-test.c index 89fa628..a1a119c 100644 --- a/tests/pnv-xscom-test.c +++ b/tests/pnv-xscom-test.c @@ -48,7 +48,7 @@ static const PnvChip pnv_chips[] = { .cpu_model = "POWER9", .xscom_base = 0x000603fc00000000ull, .xscom_core_base = 0x0ull, - .cfam_id = 0x100d104980000000ull, + .cfam_id = 0x220d104900008000ull, .first_core = 0x20, }, #endif -- cgit v1.1 From 09279d7e7b08ebfaaa40060843dbc8f33977548f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 15 Jan 2018 19:04:02 +0100 Subject: ppc/pnv: change core mask for POWER9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When addressed by XSCOM, the first core has the 0x20 chiplet ID but the CPU PIR can start at 0x0. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- tests/pnv-xscom-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/pnv-xscom-test.c b/tests/pnv-xscom-test.c index a1a119c..9d545c4 100644 --- a/tests/pnv-xscom-test.c +++ b/tests/pnv-xscom-test.c @@ -49,7 +49,7 @@ static const PnvChip pnv_chips[] = { .xscom_base = 0x000603fc00000000ull, .xscom_core_base = 0x0ull, .cfam_id = 0x220d104900008000ull, - .first_core = 0x20, + .first_core = 0x0, }, #endif }; -- cgit v1.1 From c035851ac0584e1491f6d0fa28d92a8c7a872362 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 15 Jan 2018 19:04:04 +0100 Subject: ppc/pnv: fix XSCOM core addressing on POWER9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The XSCOM base address of the core chiplet was wrongly calculated. Use the OPAL macros to fix that and do a couple of renames. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- tests/pnv-xscom-test.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) (limited to 'tests') diff --git a/tests/pnv-xscom-test.c b/tests/pnv-xscom-test.c index 9d545c4..efb7c83 100644 --- a/tests/pnv-xscom-test.c +++ b/tests/pnv-xscom-test.c @@ -21,7 +21,6 @@ typedef struct PnvChip { PnvChipType chip_type; const char *cpu_model; uint64_t xscom_base; - uint64_t xscom_core_base; uint64_t cfam_id; uint32_t first_core; } PnvChip; @@ -31,14 +30,12 @@ static const PnvChip pnv_chips[] = { .chip_type = PNV_CHIP_POWER8, .cpu_model = "POWER8", .xscom_base = 0x0003fc0000000000ull, - .xscom_core_base = 0x10000000ull, .cfam_id = 0x220ea04980000000ull, .first_core = 0x1, }, { .chip_type = PNV_CHIP_POWER8NVL, .cpu_model = "POWER8NVL", .xscom_base = 0x0003fc0000000000ull, - .xscom_core_base = 0x10000000ull, .cfam_id = 0x120d304980000000ull, .first_core = 0x1, }, @@ -47,7 +44,6 @@ static const PnvChip pnv_chips[] = { .chip_type = PNV_CHIP_POWER9, .cpu_model = "POWER9", .xscom_base = 0x000603fc00000000ull, - .xscom_core_base = 0x0ull, .cfam_id = 0x220d104900008000ull, .first_core = 0x0, }, @@ -89,16 +85,27 @@ static void test_cfam_id(const void *data) qtest_quit(global_qtest); } -#define PNV_XSCOM_EX_CORE_BASE(chip, i) \ - ((chip)->xscom_core_base | (((uint64_t)i) << 24)) + +#define PNV_XSCOM_EX_CORE_BASE 0x10000000ull +#define PNV_XSCOM_EX_BASE(core) \ + (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24)) +#define PNV_XSCOM_P9_EC_BASE(core) \ + ((uint64_t)(((core) & 0x1F) + 0x20) << 24) + #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 static void test_xscom_core(const PnvChip *chip) { - uint32_t first_core_dts0 = - PNV_XSCOM_EX_CORE_BASE(chip, chip->first_core) | - PNV_XSCOM_EX_DTS_RESULT0; - uint64_t dts0 = pnv_xscom_read(chip, first_core_dts0); + uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0; + uint64_t dts0; + + if (chip->chip_type != PNV_CHIP_POWER9) { + first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core); + } else { + first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core); + } + + dts0 = pnv_xscom_read(chip, first_core_dts0); g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull); } -- cgit v1.1