From 1e34cf9681ec549e26f30daaabc1ce58d60446f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marc=20Mar=C3=AD?= Date: Tue, 24 Feb 2015 17:34:14 +0100 Subject: libqos: Solve bug in interrupt checking when using MSIX in virtio-pci.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MSIX interrupt was always acked without checking its value, which caused a race condition. If the ISR was raised between the read and the acking, the ISR was never detected and it timed out. Signed-off-by: Marc Marí Reviewed-by: John Snow Tested-by: John Snow Message-id: 1424795655-16952-1-git-send-email-marc.mari.barcelo@gmail.com Signed-off-by: Stefan Hajnoczi Signed-off-by: Kevin Wolf --- tests/libqos/virtio-pci.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c index 046a316..f9fb924 100644 --- a/tests/libqos/virtio-pci.c +++ b/tests/libqos/virtio-pci.c @@ -142,8 +142,12 @@ static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq) return qpci_msix_pending(dev->pdev, vqpci->msix_entry); } else { data = readl(vqpci->msix_addr); - writel(vqpci->msix_addr, 0); - return data == vqpci->msix_data; + if (data == vqpci->msix_data) { + writel(vqpci->msix_addr, 0); + return true; + } else { + return false; + } } } else { return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_ISR_STATUS) & 1; @@ -162,8 +166,12 @@ static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d) return qpci_msix_pending(dev->pdev, dev->config_msix_entry); } else { data = readl(dev->config_msix_addr); - writel(dev->config_msix_addr, 0); - return data == dev->config_msix_data; + if (data == dev->config_msix_data) { + writel(dev->config_msix_addr, 0); + return true; + } else { + return false; + } } } else { return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_ISR_STATUS) & 2; -- cgit v1.1