From 4877866ee4fbd760c943577bb6d1eba489fb6c6e Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Thu, 23 May 2013 19:37:53 +0200 Subject: target-mips: fix multiplication in mipsdsp_rndq15_mul_q15_q15 Multiplication of Q15 fractional halfword vectors was incorrect in the previous implementation of mipsdsp_rndq15_mul_q15_q15. It failed to take element signs into account. This change fixes it, and it adds a test case for it. The change also removes unnecessary cast in the function mipsdsp_mul_q15_q15_overflowflag21(). Signed-off-by: Petar Jovanovic Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tests/tcg/mips/mips32-dsp/mulq_rs_ph.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'tests/tcg') diff --git a/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c index c720603..370c2a8 100644 --- a/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c +++ b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c @@ -12,7 +12,24 @@ int main() resultdsp = 1; __asm - ("mulq_rs.ph %0, %2, %3\n\t" + ("wrdsp $0\n\t" + "mulq_rs.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + rs = 0x80011234; + rt = 0x80024321; + result = 0x7FFD098C; + resultdsp = 0; + + __asm + ("wrdsp $0\n\t" + "mulq_rs.ph %0, %2, %3\n\t" "rddsp %1\n\t" : "=r"(rd), "=r"(dsp) : "r"(rs), "r"(rt) -- cgit v1.1