From 56779034530944eb6171d843f652f3fba710ed30 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 10 Jan 2011 18:30:05 +0100 Subject: tcg arm/mips/ia64: add a comment about retranslation and caches Add a comment about cache coherency and retranslation, so that people developping new targets based on existing ones are warned of the issue. Acked-by: Edgar E. Iglesias Signed-off-by: Aurelien Jarno --- tcg/arm/tcg-target.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'tcg/arm/tcg-target.c') diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 1eb5605..918e2f7 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -352,6 +352,9 @@ static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset) static inline void tcg_out_b_noaddr(TCGContext *s, int cond) { + /* We pay attention here to not modify the branch target by skipping + the corresponding bytes. This ensure that caches and memory are + kept coherent during retranslation. */ #ifdef HOST_WORDS_BIGENDIAN tcg_out8(s, (cond << 4) | 0x0a); s->code_ptr += 3; -- cgit v1.1