From 0fd8a106efb6bc2e55b3e9629b106d13a7214570 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Sun, 12 Jun 2022 18:59:34 +0900 Subject: target/openrisc: Fix memory reading in debugger In commit f0655423ca ("target/openrisc: Reorg tlb lookup") data and instruction TLB reads were combined. This, broke debugger reads where we first tried to map using the data tlb then fall back to the instruction tlb. This patch replicates this logic by first requesting a PAGE_READ protection mapping then falling back to PAGE_EXEC. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/mmu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index d7e1320..0b8afdb 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -148,7 +148,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) case SR_DME | SR_IME: /* The mmu is definitely enabled. */ excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, - PAGE_EXEC | PAGE_READ | PAGE_WRITE, + PAGE_READ, + (sr & SR_SM) != 0); + if (!excp) { + return phys_addr; + } + excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, + PAGE_EXEC, (sr & SR_SM) != 0); return excp ? -1 : phys_addr; -- cgit v1.1 From bbe6855ef80f61c6b00da22aa0cd550d79d8e381 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Wed, 15 Jun 2022 08:42:25 +0900 Subject: target/openrisc: Add interrupted CPU to log When we are tracing it's helpful to know which CPU's are getting interrupted, add that detail to the log line. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/interrupt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index e5724f5..c31c6f1 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -83,7 +83,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) [EXCP_TRAP] = "TRAP", }; - qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]); + qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n", + cs->cpu_index, + int_name[exception]); hwaddr vect_pc = exception << 8; if (env->cpucfgr & CPUCFGR_EVBARP) { -- cgit v1.1 From 6a0fc96ad2b16a264ead6b696bdb91a963450dbb Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Wed, 15 Jun 2022 08:43:56 +0900 Subject: target/openrisc: Enable MTTCG This patch enables multithread TCG for OpenRISC. Since the or1k shared syncrhonized timer can be updated from each vCPU via helpers we use a mutex to synchronize updates. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/cpu.h | 2 ++ target/openrisc/sys_helper.c | 7 ++++++- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b9584f1..1d5efa5 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -25,6 +25,8 @@ #include "hw/core/cpu.h" #include "qom/object.h" +#define TCG_GUEST_DEFAULT_MO (0) + #define TYPE_OPENRISC_CPU "or1k-cpu" OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 4867423..da88ad9 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -145,6 +145,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) break; case TO_SPR(10, 0): /* TTMR */ { + qemu_mutex_lock_iothread(); if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) { switch (rb & TTMR_M) { case TIMER_NONE: @@ -168,14 +169,16 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) env->ttmr = rb & ~TTMR_IP; cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; } - cpu_openrisc_timer_update(cpu); + qemu_mutex_unlock_iothread(); } break; case TO_SPR(10, 1): /* TTCR */ + qemu_mutex_lock_iothread(); cpu_openrisc_count_set(cpu, rb); cpu_openrisc_timer_update(cpu); + qemu_mutex_unlock_iothread(); break; #endif @@ -303,7 +306,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, return env->ttmr; case TO_SPR(10, 1): /* TTCR */ + qemu_mutex_lock_iothread(); cpu_openrisc_count_update(cpu); + qemu_mutex_unlock_iothread(); return cpu_openrisc_count_get(cpu); #endif -- cgit v1.1 From 66564c31e4e012c65c84d403c2dc14c0a754047f Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Fri, 24 Jun 2022 05:44:56 +0900 Subject: target/openrisc: Interrupt handling fixes When running SMP systems we sometimes were seeing lockups where IPI interrupts were being raised by never handled. This looks to be caused by 2 issues in the openrisc interrupt handling logic. 1. After clearing an interrupt the openrisc_cpu_set_irq handler will always clear PICSR. This is not correct as masked interrupts should still be visible in PICSR. 2. After setting PICMR (mask register) and exposed interrupts should cause an interrupt to be raised. This was not being done so add it. This patch fixes both issues. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 1 - target/openrisc/sys_helper.c | 7 +++++++ 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 41d1b2a..cb9f35f 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -98,7 +98,6 @@ static void openrisc_cpu_set_irq(void *opaque, int irq, int level) cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - cpu->env.picsr = 0; } } #endif diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index da88ad9..09b3c97 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -139,6 +139,13 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) break; case TO_SPR(9, 0): /* PICMR */ env->picmr = rb; + qemu_mutex_lock_iothread(); + if (env->picsr & env->picmr) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } + qemu_mutex_unlock_iothread(); break; case TO_SPR(9, 2): /* PICSR */ env->picsr &= ~rb; -- cgit v1.1