From df5c6a50944697bf1373582dcea719697edbc9ed Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Thu, 27 Aug 2020 13:10:32 +0200 Subject: hw/hppa: Make number of TLB and BTLB entries configurable Until now the TLB size was fixed at 256 entries. To allow operating systems to utilize more TLB entries in the future, we need to tell firmware how many TLB entries we actually support in the emulation. Firmware then reports this to the operating system via the PDC_CACHE_INFO call. This patch simply does the preparation to allow more TLB entries. Signed-off-by: Helge Deller --- target/hppa/cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 801a4fb..fb6c59d 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -196,9 +196,12 @@ struct CPUHPPAState { target_ureg shadow[7]; /* shadow registers */ /* ??? The number of entries isn't specified by the architecture. */ +#define HPPA_TLB_ENTRIES 256 +#define HPPA_BTLB_ENTRIES 0 + /* ??? Implement a unified itlb/dtlb for the moment. */ /* ??? We should use a more intelligent data structure. */ - hppa_tlb_entry tlb[256]; + hppa_tlb_entry tlb[HPPA_TLB_ENTRIES]; uint32_t tlb_last; }; -- cgit v1.1