From db9ab38b81058b41e5f469165067feea46762eee Mon Sep 17 00:00:00 2001 From: Georg Kotheimer Date: Thu, 11 Mar 2021 11:30:36 +0100 Subject: target/riscv: Use background registers also for MSTATUS_MPV The current condition for the use of background registers only considers the hypervisor load and store instructions, but not accesses from M mode via MSTATUS_MPRV+MPV. Signed-off-by: Georg Kotheimer Reviewed-by: Alistair Francis Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b15a60d..8d4a629 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -364,7 +364,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ - if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) { + if (!riscv_cpu_virt_enabled(env) && two_stage) { use_background = true; } -- cgit v1.1