From 80ac954c369e7e61bd1ed00cef07b63e11f9c734 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 23 May 2019 14:47:43 +0100 Subject: target/arm: Use extract2 for EXTR This is, after all, how we implement extract2 in tcg/aarch64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190514011129.11330-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) (limited to 'target') diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b7c5a92..2b135b9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4114,25 +4114,27 @@ static void disas_extract(DisasContext *s, uint32_t insn) } else { tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); } - } else if (rm == rn) { /* ROR */ + } else { tcg_rm = cpu_reg(s, rm); + tcg_rn = cpu_reg(s, rn); + if (sf) { - tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm); + /* Specialization to ROR happens in EXTRACT2. */ + tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm); } else { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tcg_rm); - tcg_gen_rotri_i32(tmp, tmp, imm); - tcg_gen_extu_i32_i64(tcg_rd, tmp); - tcg_temp_free_i32(tmp); - } - } else { - tcg_rm = read_cpu_reg(s, rm, sf); - tcg_rn = read_cpu_reg(s, rn, sf); - tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); - tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); - tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); - if (!sf) { - tcg_gen_ext32u_i64(tcg_rd, tcg_rd); + TCGv_i32 t0 = tcg_temp_new_i32(); + + tcg_gen_extrl_i64_i32(t0, tcg_rm); + if (rm == rn) { + tcg_gen_rotri_i32(t0, t0, imm); + } else { + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, tcg_rn); + tcg_gen_extract2_i32(t0, t0, t1, imm); + tcg_temp_free_i32(t1); + } + tcg_gen_extu_i32_i64(tcg_rd, t0); + tcg_temp_free_i32(t0); } } } -- cgit v1.1 From 87eb65a3c45c788a309986d48170a54a0d1c0705 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 23 May 2019 14:47:43 +0100 Subject: target/arm: Simplify BFXIL expansion MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mask implied by the extract is redundant with the one implied by the deposit. Also, fix spelling of BFXIL. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-id: 20190514011129.11330-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'target') diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2b135b9..42999c5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4043,8 +4043,8 @@ static void disas_bitfield(DisasContext *s, uint32_t insn) tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); return; } - /* opc == 1, BXFIL fall through to deposit */ - tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len); + /* opc == 1, BFXIL fall through to deposit */ + tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); pos = 0; } else { /* Handle the ri > si case with a deposit @@ -4062,7 +4062,7 @@ static void disas_bitfield(DisasContext *s, uint32_t insn) len = ri; } - if (opc == 1) { /* BFM, BXFIL */ + if (opc == 1) { /* BFM, BFXIL */ tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); } else { /* SBFM or UBFM: We start with zero, and we haven't modified -- cgit v1.1 From 2f143d3ad1c05e91cf2cdf5de06d59a80a95e6c8 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Thu, 23 May 2019 14:47:43 +0100 Subject: target/arm: Fix vector operation segfault MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 89e68b575 "target/arm: Use vector operations for saturation" causes this abort() when booting QEMU ARM with a Cortex-A15: 0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6 1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6 2 0x00005555559c1839 in disas_neon_data_insn (insn=, s=) at ./target/arm/translate.c:6673 3 0x00005555559c1839 in disas_neon_data_insn (s=, insn=) at ./target/arm/translate.c:6386 4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289 5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=) at ./target/arm/translate.c:13612 6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 , db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=, max_insns=) at ./accel/tcg/translator.c:96 7 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 , max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901 8 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736 9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 , cpu=0x1) at ./accel/tcg/cpu-exec.c:407 10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728 11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431 12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735 13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709 14 0x0000555555d2629a in qemu_thread_start (args=) at ./util/qemu-thread-posix.c:502 15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread. This patch ensures that we don't hit the abort() in the second switch case in disas_neon_data_insn() as we will return from the first case. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Tested-by: Alex Bennée Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com Signed-off-by: Peter Maydell --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/arm/translate.c b/target/arm/translate.c index dd053c8..298c262 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6598,13 +6598,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), rn_ofs, rm_ofs, vec_size, vec_size, (u ? uqadd_op : sqadd_op) + size); - break; + return 0; case NEON_3R_VQSUB: tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), rn_ofs, rm_ofs, vec_size, vec_size, (u ? uqsub_op : sqsub_op) + size); - break; + return 0; case NEON_3R_VMUL: /* VMUL */ if (u) { -- cgit v1.1 From 55bb1a55c72b249afa32dc1d788f230bf6a0a70d Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 23 May 2019 14:47:43 +0100 Subject: arm: Remove unnecessary includes of hw/arm/arm.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The hw/arm/arm.h header now only includes declarations relating to boot.c code, so it is only needed by Arm board or SoC code. Remove some unnecessary inclusions of it from target/arm files and from hw/intc/armv7m_nvic.c. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20190516163857.6430-3-peter.maydell@linaro.org --- target/arm/arm-semi.c | 1 - target/arm/cpu.c | 1 - target/arm/cpu64.c | 1 - target/arm/kvm.c | 1 - target/arm/kvm32.c | 1 - target/arm/kvm64.c | 1 - 6 files changed, 6 deletions(-) (limited to 'target') diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index 8b5fd7b..ddb94e0 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -29,7 +29,6 @@ #else #include "qemu-common.h" #include "exec/gdbstub.h" -#include "hw/arm/arm.h" #include "qemu/cutils.h" #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8eee1d8..9b23ac2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -30,7 +30,6 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #endif -#include "hw/arm/arm.h" #include "sysemu/sysemu.h" #include "sysemu/hw_accel.h" #include "kvm_arm.h" diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 835f73c..0ec8cd4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -25,7 +25,6 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #endif -#include "hw/arm/arm.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "kvm_arm.h" diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5995634..fe4f461 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -23,7 +23,6 @@ #include "cpu.h" #include "trace.h" #include "internals.h" -#include "hw/arm/arm.h" #include "hw/pci/pci.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 327375f..4e54e37 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -20,7 +20,6 @@ #include "sysemu/kvm.h" #include "kvm_arm.h" #include "internals.h" -#include "hw/arm/arm.h" #include "qemu/log.h" static inline void set_feature(uint64_t *features, int feature) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index e3ba149..998d21f 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -26,7 +26,6 @@ #include "sysemu/kvm.h" #include "kvm_arm.h" #include "internals.h" -#include "hw/arm/arm.h" static bool have_guest_debug; -- cgit v1.1