From ce54384405b77483f5ce06ab8dc7537299453b43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 14 Dec 2020 01:32:13 +0100 Subject: linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ISA features are usually denoted in read-only bits from CPU registers. Add the GET_FEATURE_REG_EQU() macro which checks if a CPU register has bits set to a specific value. Use the macro to check the 'Architecture Revision' level of the Config0 register, which is '2' when the Release 6 ISA is implemented. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201214003215.344522-5-f4bug@amsat.org> Signed-off-by: Laurent Vivier --- target/mips/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'target') diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3ac21d0..4cbc31c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -844,6 +844,7 @@ struct CPUMIPSState { #define CP0C0_MT 7 /* 9..7 */ #define CP0C0_VI 3 #define CP0C0_K0 0 /* 2..0 */ +#define CP0C0_AR_LENGTH 3 int32_t CP0_Config1; #define CP0C1_M 31 #define CP0C1_MMU 25 /* 30..25 */ -- cgit v1.1