From b8a4a96db3639e17ab5e5cdc14fca4b19fbf5b3b Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 16 Aug 2018 14:05:29 +0100 Subject: target/arm: Fix aa64 FCADD and FCMLA decode These insns require u=1; failed to include that in the switch cases. This probably happened during one of the rebases just before final commit. Fixes: d17b7cdcf4e Signed-off-by: Richard Henderson Reviewed-by: Laurent Desnogues Message-id: 20180810193129.1556-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'target') diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b29dc49..8ca3876 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11423,12 +11423,12 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) } feature = ARM_FEATURE_V8_DOTPROD; break; - case 0x8: /* FCMLA, #0 */ - case 0x9: /* FCMLA, #90 */ - case 0xa: /* FCMLA, #180 */ - case 0xb: /* FCMLA, #270 */ - case 0xc: /* FCADD, #90 */ - case 0xe: /* FCADD, #270 */ + case 0x18: /* FCMLA, #0 */ + case 0x19: /* FCMLA, #90 */ + case 0x1a: /* FCMLA, #180 */ + case 0x1b: /* FCMLA, #270 */ + case 0x1c: /* FCADD, #90 */ + case 0x1e: /* FCADD, #270 */ if (size == 0 || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) || (size == 3 && !is_q)) { -- cgit v1.1