From 8527b5db728b572c288fdcadb126d369040731be Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Tue, 18 Jan 2022 09:45:17 +0800 Subject: target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns Vector single-width floating-point reduction operations for EEW=32 are supported for Zve32f extension. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-15-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'target') diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index fe4ad5d..b02bb55 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2976,6 +2976,7 @@ static bool freduction_check(DisasContext *s, arg_rmrr *a) { return reduction_check(s, a) && require_rvf(s) && + require_zve32f(s) && require_zve64f(s); } -- cgit v1.1